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[RISCV][NFC] Change naming scheme for RISC-V specific DAG nodes 

Previously we had names like 'Call' or 'Tail'. This potentially clashes with
the naming scheme used elsewhere in RISCVInstrInfo.td. Many other backends
would use names like AArch64call or PPCtail. I prefer the SystemZ approach,
which uses prefixed all-lowercase names. This matches the naming scheme used
for target-independent SelectionDAG nodes.

llvm-svn: 351823
This commit is contained in:
Alex Bradbury 2019-01-22 14:05:11 +00:00
parent a4d1ffc269
commit 0a9c9a8daa
1 changed files with 48 additions and 41 deletions
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89
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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@ -16,36 +16,41 @@ include "RISCVInstrFormats.td"
// RISC-V specific DAG Nodes. // RISC-V specific DAG Nodes.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>; // Target-independent type requirements, but with target-specific formats.
def SDT_RISCVCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, def SDT_CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>; SDTCisVT<1, i32>]>;
def SDT_RISCVCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, def SDT_CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
SDTCisVT<1, i32>]>; SDTCisVT<1, i32>]>;
def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
SDTCisSameAs<0, 4>,
SDTCisSameAs<4, 5>]>;
// Target-dependent type requirements.
def SDT_RISCVCall : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
def SDT_RISCVSelectCC : SDTypeProfile<1, 5, [SDTCisSameAs<1, 2>,
SDTCisSameAs<0, 4>,
SDTCisSameAs<4, 5>]>;
def Call : SDNode<"RISCVISD::CALL", SDT_RISCVCall, // Target-independent nodes, but with target-specific formats.
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_CallSeqStart,
SDNPVariadic]>; [SDNPHasChain, SDNPOutGlue]>;
def CallSeqStart : SDNode<"ISD::CALLSEQ_START", SDT_RISCVCallSeqStart, def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_CallSeqEnd,
[SDNPHasChain, SDNPOutGlue]>; [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
def CallSeqEnd : SDNode<"ISD::CALLSEQ_END", SDT_RISCVCallSeqEnd,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; // Target-dependent nodes.
def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone, def riscv_call : SDNode<"RISCVISD::CALL", SDT_RISCVCall,
[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
def URetFlag : SDNode<"RISCVISD::URET_FLAG", SDTNone, SDNPVariadic]>;
[SDNPHasChain, SDNPOptInGlue]>; def riscv_ret_flag : SDNode<"RISCVISD::RET_FLAG", SDTNone,
def SRetFlag : SDNode<"RISCVISD::SRET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
[SDNPHasChain, SDNPOptInGlue]>; def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone,
def MRetFlag : SDNode<"RISCVISD::MRET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
[SDNPHasChain, SDNPOptInGlue]>; def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone,
def SelectCC : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC, [SDNPHasChain, SDNPOptInGlue]>;
[SDNPInGlue]>; def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone,
def Tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall, [SDNPHasChain, SDNPOptInGlue]>;
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, def riscv_selectcc : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
SDNPVariadic]>; [SDNPInGlue]>;
def riscv_tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
SDNPVariadic]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions. // Operand and SDNode transformation definitions.
@ -745,7 +750,7 @@ class SelectCC_rrirr<RegisterClass valty, RegisterClass cmpty>
: Pseudo<(outs valty:$dst), : Pseudo<(outs valty:$dst),
(ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm, (ins cmpty:$lhs, cmpty:$rhs, ixlenimm:$imm,
valty:$truev, valty:$falsev), valty:$truev, valty:$falsev),
[(set valty:$dst, (SelectCC cmpty:$lhs, cmpty:$rhs, [(set valty:$dst, (riscv_selectcc cmpty:$lhs, cmpty:$rhs,
(XLenVT imm:$imm), valty:$truev, valty:$falsev))]>; (XLenVT imm:$imm), valty:$truev, valty:$falsev))]>;
def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>; def Select_GPR_Using_CC_GPR : SelectCC_rrirr<GPR, GPR>;
@ -801,22 +806,23 @@ def : Pat<(brind (add GPR:$rs1, simm12:$imm12)),
// Define isCodeGenOnly = 0 to support parsing assembly "call" instruction. // Define isCodeGenOnly = 0 to support parsing assembly "call" instruction.
let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in let isCall = 1, Defs = [X1], isCodeGenOnly = 0 in
def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func), def PseudoCALL : Pseudo<(outs), (ins bare_symbol:$func),
[(Call tglobaladdr:$func)]> { [(riscv_call tglobaladdr:$func)]> {
let AsmString = "call\t$func"; let AsmString = "call\t$func";
} }
def : Pat<(Call texternalsym:$func), (PseudoCALL texternalsym:$func)>; def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>;
def : Pat<(URetFlag), (URET X0, X0)>; def : Pat<(riscv_uret_flag), (URET X0, X0)>;
def : Pat<(SRetFlag), (SRET X0, X0)>; def : Pat<(riscv_sret_flag), (SRET X0, X0)>;
def : Pat<(MRetFlag), (MRET X0, X0)>; def : Pat<(riscv_mret_flag), (MRET X0, X0)>;
let isCall = 1, Defs = [X1] in let isCall = 1, Defs = [X1] in
def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1), [(Call GPR:$rs1)]>, def PseudoCALLIndirect : Pseudo<(outs), (ins GPR:$rs1),
[(riscv_call GPR:$rs1)]>,
PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>; PseudoInstExpansion<(JALR X1, GPR:$rs1, 0)>;
let isBarrier = 1, isReturn = 1, isTerminator = 1 in let isBarrier = 1, isReturn = 1, isTerminator = 1 in
def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>, def PseudoRET : Pseudo<(outs), (ins), [(riscv_ret_flag)]>,
PseudoInstExpansion<(JALR X0, X1, 0)>; PseudoInstExpansion<(JALR X0, X1, 0)>;
// PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually // PseudoTAIL is a pseudo instruction similar to PseudoCALL and will eventually
@ -829,12 +835,13 @@ def PseudoTAIL : Pseudo<(outs), (ins bare_symbol:$dst), []> {
} }
let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in
def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), [(Tail GPRTC:$rs1)]>, def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1),
[(riscv_tail GPRTC:$rs1)]>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>; PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
def : Pat<(Tail (iPTR tglobaladdr:$dst)), def : Pat<(riscv_tail (iPTR tglobaladdr:$dst)),
(PseudoTAIL texternalsym:$dst)>; (PseudoTAIL texternalsym:$dst)>;
def : Pat<(Tail (iPTR texternalsym:$dst)), def : Pat<(riscv_tail (iPTR texternalsym:$dst)),
(PseudoTAIL texternalsym:$dst)>; (PseudoTAIL texternalsym:$dst)>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0, let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
@ -905,9 +912,9 @@ def : Pat<(atomic_fence (XLenVT 7), (imm)), (FENCE 0b11, 0b11)>;
// Pessimistically assume the stack pointer will be clobbered // Pessimistically assume the stack pointer will be clobbered
let Defs = [X2], Uses = [X2] in { let Defs = [X2], Uses = [X2] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(CallSeqStart timm:$amt1, timm:$amt2)]>; [(callseq_start timm:$amt1, timm:$amt2)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
[(CallSeqEnd timm:$amt1, timm:$amt2)]>; [(callseq_end timm:$amt1, timm:$amt2)]>;
} // Defs = [X2], Uses = [X2] } // Defs = [X2], Uses = [X2]
/// RV64 patterns /// RV64 patterns