[RISCV] Merge half-intrinsics-strict.ll into zvh-half-intrinsics-strict.ll. NFC
I had forgotten how we had the files partitioned.
This commit is contained in:
Craig Topper
parent
74150a0afa
commit
0d58a8cd49
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@ -1,252 +0,0 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
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; RUN: -verify-machineinstrs -target-abi ilp32f | \
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; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
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; RUN: -verify-machineinstrs -target-abi lp64f | \
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; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
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; RUN: FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
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; RUN: FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
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declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
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define half @sqrt_f16(half %a) nounwind strictfp {
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; CHECKIZFH-LABEL: sqrt_f16:
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; CHECKIZFH: # %bb.0:
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; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
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; CHECKIZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.floor.f16(half, metadata)
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define half @floor_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: floor_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call floorf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: floor_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call floorf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
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define half @ceil_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: ceil_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call ceilf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: ceil_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call ceilf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
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define half @trunc_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: trunc_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call truncf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: trunc_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call truncf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
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define half @rint_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: rint_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call rintf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: rint_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call rintf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
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define half @nearbyint_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: nearbyint_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call nearbyintf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: nearbyint_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call nearbyintf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.round.f16(half, metadata)
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define half @round_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: round_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call roundf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: round_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call roundf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
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define half @roundeven_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: roundeven_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call roundevenf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: roundeven_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call roundevenf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
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define iXLen @lrint_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: lrint_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fcvt.w.h a0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: lrint_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0
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; RV64IZFH-NEXT: ret
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%1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret iXLen %1
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}
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declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
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define iXLen @lround_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: lround_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rmm
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: lround_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
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; RV64IZFH-NEXT: ret
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%1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret iXLen %1
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}
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@ -7,10 +7,222 @@
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; RUN: | FileCheck -check-prefix=RV64IZFH %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d \
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IDZFH %s
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFH %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d \
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IDZFH %s
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; RUN: -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFH %s
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declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
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define half @sqrt_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: sqrt_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: fsqrt.h fa0, fa0
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: sqrt_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: fsqrt.h fa0, fa0
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.floor.f16(half, metadata)
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define half @floor_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: floor_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call floorf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: floor_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call floorf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
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define half @ceil_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: ceil_f16:
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; RV32IZFH: # %bb.0:
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; RV32IZFH-NEXT: addi sp, sp, -16
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; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV32IZFH-NEXT: call ceilf@plt
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; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32IZFH-NEXT: addi sp, sp, 16
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; RV32IZFH-NEXT: ret
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;
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; RV64IZFH-LABEL: ceil_f16:
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; RV64IZFH: # %bb.0:
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; RV64IZFH-NEXT: addi sp, sp, -16
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; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
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; RV64IZFH-NEXT: call ceilf@plt
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; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
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; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; RV64IZFH-NEXT: addi sp, sp, 16
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; RV64IZFH-NEXT: ret
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%1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
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ret half %1
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}
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declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
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define half @trunc_f16(half %a) nounwind strictfp {
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; RV32IZFH-LABEL: trunc_f16:
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; RV32IZFH: # %bb.0:
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||||
; RV32IZFH-NEXT: addi sp, sp, -16
|
||||
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV32IZFH-NEXT: call truncf@plt
|
||||
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IZFH-NEXT: addi sp, sp, 16
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: trunc_f16:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: addi sp, sp, -16
|
||||
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV64IZFH-NEXT: call truncf@plt
|
||||
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IZFH-NEXT: addi sp, sp, 16
|
||||
; RV64IZFH-NEXT: ret
|
||||
%1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
|
||||
ret half %1
|
||||
}
|
||||
|
||||
declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
|
||||
|
||||
define half @rint_f16(half %a) nounwind strictfp {
|
||||
; RV32IZFH-LABEL: rint_f16:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: addi sp, sp, -16
|
||||
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV32IZFH-NEXT: call rintf@plt
|
||||
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IZFH-NEXT: addi sp, sp, 16
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: rint_f16:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: addi sp, sp, -16
|
||||
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV64IZFH-NEXT: call rintf@plt
|
||||
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IZFH-NEXT: addi sp, sp, 16
|
||||
; RV64IZFH-NEXT: ret
|
||||
%1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
|
||||
ret half %1
|
||||
}
|
||||
|
||||
declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
|
||||
|
||||
define half @nearbyint_f16(half %a) nounwind strictfp {
|
||||
; RV32IZFH-LABEL: nearbyint_f16:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: addi sp, sp, -16
|
||||
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV32IZFH-NEXT: call nearbyintf@plt
|
||||
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IZFH-NEXT: addi sp, sp, 16
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: nearbyint_f16:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: addi sp, sp, -16
|
||||
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV64IZFH-NEXT: call nearbyintf@plt
|
||||
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IZFH-NEXT: addi sp, sp, 16
|
||||
; RV64IZFH-NEXT: ret
|
||||
%1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
|
||||
ret half %1
|
||||
}
|
||||
|
||||
declare half @llvm.experimental.constrained.round.f16(half, metadata)
|
||||
|
||||
define half @round_f16(half %a) nounwind strictfp {
|
||||
; RV32IZFH-LABEL: round_f16:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: addi sp, sp, -16
|
||||
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV32IZFH-NEXT: call roundf@plt
|
||||
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IZFH-NEXT: addi sp, sp, 16
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: round_f16:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: addi sp, sp, -16
|
||||
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV64IZFH-NEXT: call roundf@plt
|
||||
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IZFH-NEXT: addi sp, sp, 16
|
||||
; RV64IZFH-NEXT: ret
|
||||
%1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
|
||||
ret half %1
|
||||
}
|
||||
|
||||
declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
|
||||
|
||||
define half @roundeven_f16(half %a) nounwind strictfp {
|
||||
; RV32IZFH-LABEL: roundeven_f16:
|
||||
; RV32IZFH: # %bb.0:
|
||||
; RV32IZFH-NEXT: addi sp, sp, -16
|
||||
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
|
||||
; RV32IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV32IZFH-NEXT: call roundevenf@plt
|
||||
; RV32IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
|
||||
; RV32IZFH-NEXT: addi sp, sp, 16
|
||||
; RV32IZFH-NEXT: ret
|
||||
;
|
||||
; RV64IZFH-LABEL: roundeven_f16:
|
||||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: addi sp, sp, -16
|
||||
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
|
||||
; RV64IZFH-NEXT: fcvt.s.h fa0, fa0
|
||||
; RV64IZFH-NEXT: call roundevenf@plt
|
||||
; RV64IZFH-NEXT: fcvt.h.s fa0, fa0
|
||||
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
|
||||
; RV64IZFH-NEXT: addi sp, sp, 16
|
||||
; RV64IZFH-NEXT: ret
|
||||
%1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
|
||||
ret half %1
|
||||
}
|
||||
|
||||
declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
|
||||
|
||||
|
|
@ -24,16 +236,6 @@ define iXLen @lrint_f16(half %a) nounwind strictfp {
|
|||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: fcvt.l.h a0, fa0
|
||||
; RV64IZFH-NEXT: ret
|
||||
;
|
||||
; RV32IDZFH-LABEL: lrint_f16:
|
||||
; RV32IDZFH: # %bb.0:
|
||||
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0
|
||||
; RV32IDZFH-NEXT: ret
|
||||
;
|
||||
; RV64IDZFH-LABEL: lrint_f16:
|
||||
; RV64IDZFH: # %bb.0:
|
||||
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
|
||||
; RV64IDZFH-NEXT: ret
|
||||
%1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
|
||||
ret iXLen %1
|
||||
}
|
||||
|
|
@ -50,16 +252,6 @@ define iXLen @lround_f16(half %a) nounwind strictfp {
|
|||
; RV64IZFH: # %bb.0:
|
||||
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
|
||||
; RV64IZFH-NEXT: ret
|
||||
;
|
||||
; RV32IDZFH-LABEL: lround_f16:
|
||||
; RV32IDZFH: # %bb.0:
|
||||
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
|
||||
; RV32IDZFH-NEXT: ret
|
||||
;
|
||||
; RV64IDZFH-LABEL: lround_f16:
|
||||
; RV64IDZFH: # %bb.0:
|
||||
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
|
||||
; RV64IDZFH-NEXT: ret
|
||||
%1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
|
||||
ret iXLen %1
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue