Use the correct shift amount type.

llvm-svn: 126684
2011-02-28 21:10:10 +00:00 · 2011-02-28 21:10:10 +00:00 · 0dc63104c6
parent 4f4df81861
commit 0dc63104c6
1 changed files with 1 additions and 1 deletions
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@ -226,7 +226,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {

  unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
  return DAG.getNode(ISD::SRL, dl, NVT, DAG.getNode(ISD::BSWAP, dl, NVT, Op),
-                     DAG.getConstant(DiffBits, TLI.getPointerTy()));
+                     DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT)));
 }

 SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) {