[x86] add tests for potentially miscompiling cvttp2si (PR37751); NFC
llvm-svn: 334367
This commit is contained in:
Sanjay Patel
parent
3cce6a7ed9
commit
15bee8f1c0
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
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; PR37551 - https://bugs.llvm.org/show_bug.cgi?id=37751
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; We can't combine into 'round' instructions because the behavior is different for out-of-range values.
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declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>)
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declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>)
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define <8 x float> @float_to_int_to_float_mem_v8f32(<8 x float>* %p) {
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; AVX1-LABEL: float_to_int_to_float_mem_v8f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vroundps $11, (%rdi), %ymm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: float_to_int_to_float_mem_v8f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vmovups (%rdi), %ymm0
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; AVX512-NEXT: vroundps $11, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%x = load <8 x float>, <8 x float>* %p, align 16
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%fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)
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%sitofp = sitofp <8 x i32> %fptosi to <8 x float>
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ret <8 x float> %sitofp
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}
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define <8 x float> @float_to_int_to_float_reg_v8f32(<8 x float> %x) {
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; AVX-LABEL: float_to_int_to_float_reg_v8f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vroundps $11, %ymm0, %ymm0
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; AVX-NEXT: retq
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%fptosi = tail call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %x)
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%sitofp = sitofp <8 x i32> %fptosi to <8 x float>
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ret <8 x float> %sitofp
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}
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define <4 x double> @float_to_int_to_float_mem_v4f64(<4 x double>* %p) {
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; AVX1-LABEL: float_to_int_to_float_mem_v4f64:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vroundpd $11, (%rdi), %ymm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: float_to_int_to_float_mem_v4f64:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vmovupd (%rdi), %ymm0
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; AVX512-NEXT: vroundpd $11, %ymm0, %ymm0
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; AVX512-NEXT: retq
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%x = load <4 x double>, <4 x double>* %p, align 16
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%fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x double>
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ret <4 x double> %sitofp
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}
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define <4 x double> @float_to_int_to_float_reg_v4f64(<4 x double> %x) {
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; AVX-LABEL: float_to_int_to_float_reg_v4f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vroundpd $11, %ymm0, %ymm0
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; AVX-NEXT: retq
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%fptosi = tail call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x double>
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ret <4 x double> %sitofp
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}
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=sse4.1 | FileCheck %s --check-prefixes=SSE
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx | FileCheck %s --check-prefixes=AVX,AVX1
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512f,avx512vl | FileCheck %s --check-prefixes=AVX,AVX512
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; PR37551 - https://bugs.llvm.org/show_bug.cgi?id=37751
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; We can't combine into 'round' instructions because the behavior is different for out-of-range values.
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declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>)
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declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>)
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define <4 x float> @float_to_int_to_float_mem_v4f32(<4 x float>* %p) {
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; SSE-LABEL: float_to_int_to_float_mem_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: roundps $11, (%rdi), %xmm0
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; SSE-NEXT: retq
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;
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; AVX1-LABEL: float_to_int_to_float_mem_v4f32:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vroundps $11, (%rdi), %xmm0
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; AVX1-NEXT: retq
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;
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; AVX512-LABEL: float_to_int_to_float_mem_v4f32:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vmovaps (%rdi), %xmm0
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; AVX512-NEXT: vroundps $11, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%x = load <4 x float>, <4 x float>* %p, align 16
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x float>
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ret <4 x float> %sitofp
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}
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define <4 x float> @float_to_int_to_float_reg_v4f32(<4 x float> %x) {
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; SSE-LABEL: float_to_int_to_float_reg_v4f32:
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; SSE: # %bb.0:
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; SSE-NEXT: roundps $11, %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_v4f32:
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; AVX: # %bb.0:
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; AVX-NEXT: vroundps $11, %xmm0, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %x)
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%sitofp = sitofp <4 x i32> %fptosi to <4 x float>
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ret <4 x float> %sitofp
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}
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define <2 x double> @float_to_int_to_float_mem_v2f64(<2 x double>* %p) {
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; SSE-LABEL: float_to_int_to_float_mem_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttpd2dq (%rdi), %xmm0
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_mem_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttpd2dqx (%rdi), %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: retq
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%x = load <2 x double>, <2 x double>* %p, align 16
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %x)
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%concat = shufflevector <4 x i32> %fptosi, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%sitofp = sitofp <2 x i32> %concat to <2 x double>
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ret <2 x double> %sitofp
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}
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define <2 x double> @float_to_int_to_float_reg_v2f64(<2 x double> %x) {
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; SSE-LABEL: float_to_int_to_float_reg_v2f64:
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; SSE: # %bb.0:
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; SSE-NEXT: cvttpd2dq %xmm0, %xmm0
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; SSE-NEXT: cvtdq2pd %xmm0, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: float_to_int_to_float_reg_v2f64:
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; AVX: # %bb.0:
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; AVX-NEXT: vcvttpd2dq %xmm0, %xmm0
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; AVX-NEXT: vcvtdq2pd %xmm0, %xmm0
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; AVX-NEXT: retq
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%fptosi = tail call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %x)
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%concat = shufflevector <4 x i32> %fptosi, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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%sitofp = sitofp <2 x i32> %concat to <2 x double>
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ret <2 x double> %sitofp
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}
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