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[x86] fix test specifications and auto-generate checks 

llvm-svn: 289492
This commit is contained in:
Sanjay Patel 2016-12-12 23:15:15 +00:00
parent 024a17b06d
commit 1740526e99
1 changed files with 38 additions and 29 deletions
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67
llvm/test/CodeGen/X86/SwizzleShuff.ll
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@ -1,11 +1,14 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s
; Check that we perform a scalar XOR on i32.
; CHECK: pull_bitcast
; CHECK: xorl
; CHECK: ret
define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
define void @pull_bitcast(<4 x i8>* %pA, <4 x i8>* %pB) {
; CHECK-LABEL: pull_bitcast:
; CHECK: # BB#0:
; CHECK-NEXT: movl (%rsi), %eax
; CHECK-NEXT: xorl %eax, (%rdi)
; CHECK-NEXT: retq
%A = load <4 x i8>, <4 x i8>* %pA
%B = load <4 x i8>, <4 x i8>* %pB
%C = xor <4 x i8> %A, %B
@ -13,15 +16,16 @@ define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
ret void
}
; CHECK: multi_use_swizzle
; CHECK: pshufd
; CHECK-NEXT: pshufd
; CHECK-NEXT: pblendw
; CHECK-NEXT: pshufd
; CHECK-NEXT: pshufd
; CHECK-NEXT: pxor
; CHECK-NEXT: ret
define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
define <4 x i32> @multi_use_swizzle(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: multi_use_swizzle:
; CHECK: # BB#0:
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = mem[0,1,1,2]
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = mem[1,1,2,3]
; CHECK-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]
; CHECK-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,3,2,2]
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,0,2]
; CHECK-NEXT: vpxor %xmm0, %xmm1, %xmm0
; CHECK-NEXT: retq
%A = load <4 x i32>, <4 x i32>* %pA
%B = load <4 x i32>, <4 x i32>* %pB
%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
@ -31,10 +35,15 @@ define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
ret <4 x i32> %R
}
; CHECK: pull_bitcast2
; CHECK: xorl
; CHECK: ret
define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
define <4 x i8> @pull_bitcast2(<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
; CHECK-LABEL: pull_bitcast2:
; CHECK: # BB#0:
; CHECK-NEXT: movl (%rdi), %eax
; CHECK-NEXT: movl %eax, (%rdx)
; CHECK-NEXT: xorl (%rsi), %eax
; CHECK-NEXT: vmovd %eax, %xmm0
; CHECK-NEXT: movl %eax, (%rdi)
; CHECK-NEXT: retq
%A = load <4 x i8>, <4 x i8>* %pA
store <4 x i8> %A, <4 x i8>* %pC
%B = load <4 x i8>, <4 x i8>* %pB
@ -43,12 +52,11 @@ define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
ret <4 x i8> %C
}
; CHECK: reverse_1
; CHECK-NOT: pshufd
; CHECK: ret
define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
define <4 x i32> @reverse_1(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: reverse_1:
; CHECK: # BB#0:
; CHECK-NEXT: vmovaps (%rdi), %xmm0
; CHECK-NEXT: retq
%A = load <4 x i32>, <4 x i32>* %pA
%B = load <4 x i32>, <4 x i32>* %pB
%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@ -56,14 +64,15 @@ define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
ret <4 x i32> %S1
}
; CHECK: no_reverse_shuff
; CHECK: pshufd
; CHECK: ret
define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
define <4 x i32> @no_reverse_shuff(<4 x i32>* %pA, <4 x i32>* %pB) {
; CHECK-LABEL: no_reverse_shuff:
; CHECK: # BB#0:
; CHECK-NEXT: vpshufd {{.*#+}} xmm0 = mem[2,3,2,3]
; CHECK-NEXT: retq
%A = load <4 x i32>, <4 x i32>* %pA
%B = load <4 x i32>, <4 x i32>* %pB
%S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
%S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
ret <4 x i32> %S1
}