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[InstCombine] Add m_Negative pattern matching 

Allows us to add non-uniform constant vector support for "X urem C -> X < C ? X : X - C, where C >= signbit."

llvm-svn: 324631
This commit is contained in:
Simon Pilgrim 2018-02-08 18:36:01 +00:00
parent 7aee1a838e
commit 1889f26b94
3 changed files with 13 additions and 4 deletions
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8
llvm/include/llvm/IR/PatternMatch.h
View File

@ -339,6 +339,14 @@ template <typename Predicate> struct api_pred_ty : public Predicate {
} }
}; };
struct is_negative {
bool isValue(const APInt &C) { return C.isNegative(); }
};
/// \brief Match an integer or vector of negative values.
inline cst_pred_ty<is_negative> m_Negative() { return cst_pred_ty<is_negative>(); }
inline api_pred_ty<is_negative> m_Negative(const APInt *&V) { return V; }
struct is_power2 { struct is_power2 {
bool isValue(const APInt &C) { return C.isPowerOf2(); } bool isValue(const APInt &C) { return C.isPowerOf2(); }
}; };

3
llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
View File

@ -1604,8 +1604,7 @@ Instruction *InstCombiner::visitURem(BinaryOperator &I) {
} }
// X urem C -> X < C ? X : X - C, where C >= signbit. // X urem C -> X < C ? X : X - C, where C >= signbit.
const APInt *DivisorC; if (match(Op1, m_Negative())) {
if (match(Op1, m_APInt(DivisorC)) && DivisorC->isNegative()) {
Value *Cmp = Builder.CreateICmpULT(Op0, Op1); Value *Cmp = Builder.CreateICmpULT(Op0, Op1);
Value *Sub = Builder.CreateSub(Op0, Op1); Value *Sub = Builder.CreateSub(Op0, Op1);
return SelectInst::Create(Cmp, Op0, Sub); return SelectInst::Create(Cmp, Op0, Sub);

6
llvm/test/Transforms/InstCombine/vector-urem.ll
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@ -59,8 +59,10 @@ define <4 x i32> @test_v4i32_negconstsplat(<4 x i32> %a0) {
define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) { define <4 x i32> @test_v4i32_negconst(<4 x i32> %a0) {
; CHECK-LABEL: @test_v4i32_negconst( ; CHECK-LABEL: @test_v4i32_negconst(
; CHECK-NEXT: [[TMP1:%.*]] = urem <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9> ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult <4 x i32> [[A0:%.*]], <i32 -3, i32 -5, i32 -7, i32 -9>
; CHECK-NEXT: ret <4 x i32> [[TMP1]] ; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i32> [[A0]], <i32 3, i32 5, i32 7, i32 9>
; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A0]], <4 x i32> [[TMP2]]
; CHECK-NEXT: ret <4 x i32> [[TMP3]]
; ;
%1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9> %1 = urem <4 x i32> %a0, <i32 -3, i32 -5, i32 -7, i32 -9>
ret <4 x i32> %1 ret <4 x i32> %1