Fixed expression evaluation with convenience registers.
- Also improved test coverage for passing tests to include expr/x and a sanity check for $eax as the lower half of $rax. llvm-svn: 181727
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@ -382,7 +382,7 @@ namespace lldb_private {
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RegisterValue::Type m_type;
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RegisterValue::Type m_type;
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union
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union
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{
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{
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uint8_t uint8;
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uint8_t uint8;
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uint16_t uint16;
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uint16_t uint16;
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uint32_t uint32;
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uint32_t uint32;
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uint64_t uint64;
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uint64_t uint64;
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@ -547,6 +547,8 @@ RegisterContext_x86_64::GetRegisterCount()
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const RegisterInfo *
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const RegisterInfo *
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RegisterContext_x86_64::GetRegisterInfo()
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RegisterContext_x86_64::GetRegisterInfo()
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{
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{
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// Commonly, this method is overridden and g_register_infos is copied and specialized.
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// So, use GetRegisterInfo() rather than g_register_infos in this scope.
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return g_register_infos;
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return g_register_infos;
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}
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}
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@ -680,6 +682,9 @@ RegisterContext_x86_64::IsRegisterSetAvailable(size_t set_index)
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bool
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bool
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RegisterContext_x86_64::ReadRegister(const RegisterInfo *reg_info, RegisterValue &value)
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RegisterContext_x86_64::ReadRegister(const RegisterInfo *reg_info, RegisterValue &value)
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{
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{
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if (!reg_info)
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return false;
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const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
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const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
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if (IsFPR(reg, m_fpr_type)) {
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if (IsFPR(reg, m_fpr_type)) {
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@ -688,8 +693,14 @@ RegisterContext_x86_64::ReadRegister(const RegisterInfo *reg_info, RegisterValue
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}
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}
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else {
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else {
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ProcessMonitor &monitor = GetMonitor();
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ProcessMonitor &monitor = GetMonitor();
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return monitor.ReadRegisterValue(m_thread.GetID(), GetRegisterOffset(reg),
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bool success = monitor.ReadRegisterValue(m_thread.GetID(), GetRegisterOffset(reg),
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GetRegisterName(reg), GetRegisterSize(reg), value);
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GetRegisterName(reg), GetRegisterSize(reg), value);
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// If an i386 register should be parsed from an x86_64 register...
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if (success && reg >= k_first_i386 && reg <= k_last_i386)
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if (value.GetByteSize() > reg_info->byte_size)
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value.SetType(reg_info); // ...use the type specified by reg_info rather than the uint64_t default
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return success;
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}
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}
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if (reg_info->encoding == eEncodingVector) {
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if (reg_info->encoding == eEncodingVector) {
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@ -43,7 +43,8 @@ enum
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gpr_ss,
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gpr_ss,
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gpr_ds,
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gpr_ds,
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gpr_es,
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gpr_es,
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gpr_eax,
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k_first_i386,
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gpr_eax = k_first_i386,
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gpr_ebx,
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gpr_ebx,
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gpr_ecx,
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gpr_ecx,
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gpr_edx,
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gpr_edx,
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@ -52,8 +53,9 @@ enum
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gpr_ebp,
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gpr_ebp,
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gpr_esp,
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gpr_esp,
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gpr_eip,
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gpr_eip,
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gpr_eflags,
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gpr_eflags, // eRegisterKindLLDB == 33
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k_last_gpr = gpr_eflags, // eRegisterKindLLDB == 33
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k_last_i386 = gpr_eflags,
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k_last_gpr = gpr_eflags,
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k_first_fpr,
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k_first_fpr,
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fpu_fcw = k_first_fpr,
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fpu_fcw = k_first_fpr,
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@ -186,6 +186,12 @@ class RegisterCommandsTestCase(TestBase):
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"""Test expression evaluation with commands related to registers."""
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"""Test expression evaluation with commands related to registers."""
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self.common_setup()
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self.common_setup()
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self.expect("expr/x $eax",
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substrs = ['unsigned int', ' = 0x'])
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self.expect("expr -- ($rax & 0xffffffff) == $eax",
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substrs = ['true'])
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self.expect("expr $xmm0",
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self.expect("expr $xmm0",
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substrs = ['vector_type'])
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substrs = ['vector_type'])
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