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Replace copyRegToReg with copyPhysReg for CellSPU. 

llvm-svn: 108084
This commit is contained in:
Jakob Stoklund Olesen 2010-07-11 07:31:03 +00:00
parent 0d611979a8
commit 1dba6814c9
2 changed files with 10 additions and 34 deletions
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32
llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
View File

@ -249,40 +249,18 @@ SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
return 0; return 0;
} }
bool SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB, void SPUInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC, bool KillSrc) const
const TargetRegisterClass *SrcRC,
DebugLoc DL) const
{ {
// We support cross register class moves for our aliases, such as R3 in any // We support cross register class moves for our aliases, such as R3 in any
// reg class to any other reg class containing R3. This is required because // reg class to any other reg class containing R3. This is required because
// we instruction select bitconvert i64 -> f64 as a noop for example, so our // we instruction select bitconvert i64 -> f64 as a noop for example, so our
// types have no specific meaning. // types have no specific meaning.
if (DestRC == SPU::R8CRegisterClass) { BuildMI(MBB, I, DL, get(SPU::LRr128), DestReg)
BuildMI(MBB, MI, DL, get(SPU::LRr8), DestReg).addReg(SrcReg); .addReg(SrcReg, getKillRegState(KillSrc));
} else if (DestRC == SPU::R16CRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRr16), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32CRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRr32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R32FPRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRf32), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64CRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRr64), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::R64FPRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRf64), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::GPRCRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRr128), DestReg).addReg(SrcReg);
} else if (DestRC == SPU::VECREGRegisterClass) {
BuildMI(MBB, MI, DL, get(SPU::LRv16i8), DestReg).addReg(SrcReg);
} else {
// Attempt to copy unknown/unsupported register class!
return false;
}
return true;
} }
void void

8
llvm/lib/Target/CellSPU/SPUInstrInfo.h
View File

@ -56,12 +56,10 @@ namespace llvm {
unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB, virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC, bool KillSrc) const;
const TargetRegisterClass *SrcRC,
DebugLoc DL) const;
//! Store a register to a stack slot, based on its register class. //! Store a register to a stack slot, based on its register class.
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, virtual void storeRegToStackSlot(MachineBasicBlock &MBB,