[msan] Add test for vector abs intrinsic
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Vitaly Buka
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cb9cfa0d2f
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1fd9a146d3
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -S -msan-check-access-address=0 -passes=msan 2>&1 | FileCheck %s
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; RUN: opt < %s -S -msan-check-access-address=0 -msan | FileCheck %s
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; RUN: opt < %s -S -msan-check-access-address=0 -msan-track-origins=2 -passes=msan 2>&1 | FileCheck %s --check-prefixes=CHECK,ORIGIN
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; RUN: opt < %s -S -msan-check-access-address=0 -msan-track-origins=2 -msan | FileCheck %s --check-prefixes=CHECK,ORIGIN
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target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define <4 x i64> @test_mm256_abs_epi8(<4 x i64> noundef %a) local_unnamed_addr #0 {
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; CHECK-LABEL: @test_mm256_abs_epi8(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4
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; CHECK: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <32 x i8>
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <32 x i8>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <32 x i8> [[TMP2]] to i256
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof !2
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; CHECK: call void @__msan_warning_with_origin_noreturn
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; CHECK: unreachable
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; CHECK: [[TMP7:%.*]] = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> [[TMP3]], i1 false)
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast <32 x i8> [[TMP7]] to <4 x i64>
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; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4
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; CHECK: ret <4 x i64> [[TMP8]]
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;
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entry:
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%0 = bitcast <4 x i64> %a to <32 x i8>
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%1 = tail call <32 x i8> @llvm.abs.v32i8(<32 x i8> %0, i1 false)
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%2 = bitcast <32 x i8> %1 to <4 x i64>
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ret <4 x i64> %2
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}
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define <4 x i64> @test_mm256_abs_epi16(<4 x i64> %a) local_unnamed_addr #0 {
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; CHECK-LABEL: @test_mm256_abs_epi16(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4
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; CHECK: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <16 x i16>
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <16 x i16>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i16> [[TMP2]] to i256
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof !2
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; CHECK: call void @__msan_warning_with_origin_noreturn
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; CHECK: unreachable
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; CHECK: [[TMP7:%.*]] = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> [[TMP3]], i1 false)
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast <16 x i16> [[TMP7]] to <4 x i64>
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; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4
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; CHECK: ret <4 x i64> [[TMP8]]
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;
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entry:
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%0 = bitcast <4 x i64> %a to <16 x i16>
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%1 = tail call <16 x i16> @llvm.abs.v16i16(<16 x i16> %0, i1 false)
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%2 = bitcast <16 x i16> %1 to <4 x i64>
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ret <4 x i64> %2
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}
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define <4 x i64> @test_mm256_abs_epi32(<4 x i64> %a) local_unnamed_addr #0 {
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; CHECK-LABEL: @test_mm256_abs_epi32(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, <4 x i64>* bitcast ([100 x i64]* @__msan_param_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: [[TMP1:%.*]] = load i32, i32* getelementptr inbounds ([200 x i32], [200 x i32]* @__msan_param_origin_tls, i32 0, i32 0), align 4
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; CHECK: [[TMP2:%.*]] = bitcast <4 x i64> [[TMP0]] to <8 x i32>
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; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i64> [[A:%.*]] to <8 x i32>
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i32> [[TMP2]] to i256
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; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i256 [[TMP4]], 0
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; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof !2
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; CHECK: call void @__msan_warning_with_origin_noreturn
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; CHECK: unreachable
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; CHECK: [[TMP7:%.*]] = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> [[TMP3]], i1 false)
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; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i32> [[TMP7]] to <4 x i64>
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; CHECK-NEXT: store <4 x i64> zeroinitializer, <4 x i64>* bitcast ([100 x i64]* @__msan_retval_tls to <4 x i64>*), align 8
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; ORIGIN-NEXT: store i32 0, i32* @__msan_retval_origin_tls, align 4
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; CHECK: ret <4 x i64> [[TMP8]]
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;
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <8 x i32> @llvm.abs.v8i32(<8 x i32> %0, i1 false)
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%2 = bitcast <8 x i32> %1 to <4 x i64>
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ret <4 x i64> %2
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}
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declare <32 x i8> @llvm.abs.v32i8(<32 x i8>, i1 immarg) #1
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declare <16 x i16> @llvm.abs.v16i16(<16 x i16>, i1 immarg) #1
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declare <8 x i32> @llvm.abs.v8i32(<8 x i32>, i1 immarg) #1
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attributes #0 = { nounwind readnone sanitize_memory }
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attributes #1 = { nounwind readnone speculatable willreturn }
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!llvm.module.flags = !{!0}
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!llvm.ident = !{!1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{!"clang version 12.0.0"}
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