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[X86][AVX] Reduce unary target shuffles width if the upper elements aren't demanded.

This commit is contained in:
Simon Pilgrim 2020-05-31 20:19:24 +01:00
parent 8f2f613a6e
commit 22e50833e9
4 changed files with 31 additions and 36 deletions
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5
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -36908,6 +36908,11 @@ bool X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(
return TLO.CombineTo(Op, insertSubVector(TLO.DAG.getUNDEF(VT), Src, 0,
TLO.DAG, DL, ExtSizeInBits));
}
// Target unary shuffles by immediate:
case X86ISD::PSHUFD:
case X86ISD::PSHUFLW:
case X86ISD::PSHUFHW:
case X86ISD::VPERMILPI:
// Byte shifts by immediate.
case X86ISD::VSHLDQ:
case X86ISD::VSRLDQ:

32
llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
View File

@ -7742,7 +7742,7 @@ define i64 @test_mm512_reduce_max_epi64(<8 x i64> %__W) {
; X86-NEXT: vpmaxsq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -7755,7 +7755,7 @@ define i64 @test_mm512_reduce_max_epi64(<8 x i64> %__W) {
; X64-NEXT: vpmaxsq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -7781,7 +7781,7 @@ define i64 @test_mm512_reduce_max_epu64(<8 x i64> %__W) {
; X86-NEXT: vpmaxuq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -7794,7 +7794,7 @@ define i64 @test_mm512_reduce_max_epu64(<8 x i64> %__W) {
; X64-NEXT: vpmaxuq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -7867,7 +7867,7 @@ define i64 @test_mm512_reduce_min_epi64(<8 x i64> %__W) {
; X86-NEXT: vpminsq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -7880,7 +7880,7 @@ define i64 @test_mm512_reduce_min_epi64(<8 x i64> %__W) {
; X64-NEXT: vpminsq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -7906,7 +7906,7 @@ define i64 @test_mm512_reduce_min_epu64(<8 x i64> %__W) {
; X86-NEXT: vpminuq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -7919,7 +7919,7 @@ define i64 @test_mm512_reduce_min_epu64(<8 x i64> %__W) {
; X64-NEXT: vpminuq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -7996,7 +7996,7 @@ define i64 @test_mm512_mask_reduce_max_epi64(i8 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpmaxsq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -8012,7 +8012,7 @@ define i64 @test_mm512_mask_reduce_max_epi64(i8 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpmaxsq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpmaxsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -8043,7 +8043,7 @@ define i64 @test_mm512_mask_reduce_max_epu64(i8 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -8058,7 +8058,7 @@ define i64 @test_mm512_mask_reduce_max_epu64(i8 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpmaxuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -8146,7 +8146,7 @@ define i64 @test_mm512_mask_reduce_min_epi64(i8 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpminsq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -8162,7 +8162,7 @@ define i64 @test_mm512_mask_reduce_min_epi64(i8 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpminsq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpminsq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper
@ -8194,7 +8194,7 @@ define i64 @test_mm512_mask_reduce_min_epu64(i8 zeroext %__M, <8 x i64> %__W) {
; X86-NEXT: vpminuq %zmm0, %zmm1, %zmm0
; X86-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X86-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X86-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X86-NEXT: vmovd %xmm0, %eax
; X86-NEXT: vpextrd $1, %xmm0, %edx
@ -8210,7 +8210,7 @@ define i64 @test_mm512_mask_reduce_min_epu64(i8 zeroext %__M, <8 x i64> %__W) {
; X64-NEXT: vpminuq %zmm0, %zmm1, %zmm0
; X64-NEXT: vpermq {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5]
; X64-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vpshufd {{.*#+}} zmm1 = zmm0[2,3,0,1,6,7,4,5,10,11,8,9,14,15,12,13]
; X64-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-NEXT: vpminuq %zmm1, %zmm0, %zmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vzeroupper

27
llvm/test/CodeGen/X86/vector-reduce-mul.ll
View File

@ -1969,8 +1969,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX2-NEXT: vpmullw %xmm2, %xmm1, %xmm1
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2052,8 +2051,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX512DQ-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512DQ-NEXT: vpmullw %xmm2, %xmm1, %xmm1
; AVX512DQ-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX512DQ-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512DQ-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512DQ-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512DQ-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2079,8 +2077,7 @@ define i8 @test_v32i8(<32 x i8> %a0) {
; AVX512DQVL-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512DQVL-NEXT: vpmullw %xmm2, %xmm1, %xmm1
; AVX512DQVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512DQVL-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX512DQVL-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
; AVX512DQVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512DQVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512DQVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512DQVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2238,8 +2235,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
; AVX2-NEXT: vpmullw %xmm0, %xmm3, %xmm0
; AVX2-NEXT: vpmullw %xmm0, %xmm2, %xmm0
; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm2
; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[2,3,2,3,6,7,6,7]
; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX2-NEXT: vpmullw %xmm2, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm2 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX2-NEXT: vpmullw %xmm2, %xmm0, %xmm0
@ -2274,8 +2270,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512BW-NEXT: vpmullw %xmm2, %xmm1, %xmm1
; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX512BW-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
; AVX512BW-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2311,8 +2306,7 @@ define i8 @test_v64i8(<64 x i8> %a0) {
; AVX512BWVL-NEXT: vpunpckhbw {{.*#+}} xmm2 = xmm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX512BWVL-NEXT: vpmullw %xmm2, %xmm1, %xmm1
; AVX512BWVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
; AVX512BWVL-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512BWVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512BWVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2608,8 +2602,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm3
; AVX2-NEXT: vpmullw %xmm1, %xmm3, %xmm1
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm1
; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[2,3,2,3,6,7,6,7]
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX2-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2647,8 +2640,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX512BW-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
; AVX512BW-NEXT: vpmullw %xmm0, %xmm1, %xmm0
; AVX512BW-NEXT: vpmullw %xmm0, %xmm2, %xmm0
; AVX512BW-NEXT: vpand %xmm3, %xmm0, %xmm1
; AVX512BW-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
; AVX512BW-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BW-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
@ -2687,8 +2679,7 @@ define i8 @test_v128i8(<128 x i8> %a0) {
; AVX512BWVL-NEXT: vpunpckhbw {{.*#+}} xmm0 = xmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15]
; AVX512BWVL-NEXT: vpmullw %xmm0, %xmm1, %xmm0
; AVX512BWVL-NEXT: vpmullw %xmm0, %xmm2, %xmm0
; AVX512BWVL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm1
; AVX512BWVL-NEXT: vpshufd {{.*#+}} zmm1 = zmm1[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero,xmm0[8],zero,xmm0[10],zero,xmm0[12],zero,xmm0[14],zero
; AVX512BWVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0
; AVX512BWVL-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[4],zero,xmm0[6],zero,zero,zero,zero,zero,xmm0[12],zero,xmm0[14],zero,zero,zero,zero,zero
; AVX512BWVL-NEXT: vpmullw %xmm1, %xmm0, %xmm0

3
llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
View File

@ -145,8 +145,7 @@ define <8 x float> @combine_vpermilvar_vperm2f128_zero_8f32(<8 x float> %a0) {
define <4 x double> @combine_vperm2f128_vpermilvar_as_vpblendpd(<4 x double> %a0) {
; CHECK-LABEL: combine_vperm2f128_vpermilvar_as_vpblendpd:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
; CHECK-NEXT: vmovapd %xmm0, %xmm0
; CHECK-NEXT: vpermilpd {{.*#+}} xmm0 = xmm0[1,0]
; CHECK-NEXT: vpermilpd {{.*#+}} ymm0 = ymm0[1,0,3,2]
; CHECK-NEXT: ret{{[l|q]}}
%1 = tail call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 2, i64 0>)