From 2a30aeb01073523109f72b4cb5b51a88839e3daa Mon Sep 17 00:00:00 2001 From: Jatin Bhateja Date: Sun, 9 Jun 2019 09:59:26 +0000 Subject: [PATCH] [X86] NFCI : Comment updation for EVEX to VEX translation. Reviewers: llvm-commits, jbhateja Reviewed By: jbhateja Subscribers: llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63055 llvm-svn: 362898 --- llvm/lib/Target/X86/X86EvexToVex.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86EvexToVex.cpp b/llvm/lib/Target/X86/X86EvexToVex.cpp index ec470889b6c9..e92fe4ab248d 100644 --- a/llvm/lib/Target/X86/X86EvexToVex.cpp +++ b/llvm/lib/Target/X86/X86EvexToVex.cpp @@ -12,9 +12,9 @@ /// are encoded using the EVEX prefix and if possible replaces them by their /// corresponding VEX encoding which is usually shorter by 2 bytes. /// EVEX instructions may be encoded via the VEX prefix when the AVX-512 -/// instruction has a corresponding AVX/AVX2 opcode and when it does not -/// use the xmm or the mask registers or xmm/ymm registers with indexes -/// higher than 15. +/// instruction has a corresponding AVX/AVX2 opcode, when vector length +/// accessed by instruction is less than 512 bits and when it does not use +// the xmm or the mask registers or xmm/ymm registers with indexes higher than 15. /// The pass applies code reduction on the generated code for AVX-512 instrs. // //===----------------------------------------------------------------------===//