[X86] Add NEG and NOT test cases to atomic_mi.ll in preparation for fixing the FIXME in X86InstrCompiler.td to make these work for atomic load/store.
llvm-svn: 338781
This commit is contained in:
Craig Topper
parent
122171e235
commit
2deeeae2a5
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@ -1503,6 +1503,270 @@ define void @dec_32_seq_cst(i32* %p) {
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ret void
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}
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; ----- NOT -----
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define void @not_8(i8* %p) {
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; X64-LABEL: not_8:
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; X64: # %bb.0:
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; X64-NEXT: xorb $-1, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: not_8:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: xorb $-1, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i8, i8* %p seq_cst, align 1
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%2 = xor i8 %1, -1
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @not_16(i16* %p) {
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; Currently the transformation is not done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: not_16:
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; X64: # %bb.0:
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; X64-NEXT: movw (%rdi), %ax
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; X64-NEXT: notl %eax
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; X64-NEXT: movw %ax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: not_16:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movw (%eax), %cx
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; X32-NEXT: notl %ecx
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; X32-NEXT: movw %cx, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i16, i16* %p acquire, align 2
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%2 = xor i16 %1, -1
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @not_32(i32* %p) {
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; X64-LABEL: not_32:
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; X64: # %bb.0:
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; X64-NEXT: xorl $-1, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: not_32:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: xorl $-1, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i32, i32* %p acquire, align 4
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%2 = xor i32 %1, -1
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store atomic i32 %2, i32* %p monotonic, align 4
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ret void
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}
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define void @not_64(i64* %p) {
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; X64-LABEL: not_64:
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; X64: # %bb.0:
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; X64-NEXT: xorq $-1, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: not_64:
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; X32: # %bb.0:
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; X32-NEXT: pushl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: pushl %esi
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; X32-NEXT: .cfi_def_cfa_offset 12
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; X32-NEXT: .cfi_offset %esi, -12
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; X32-NEXT: .cfi_offset %ebx, -8
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: xorl %ecx, %ecx
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; X32-NEXT: xorl %ebx, %ebx
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; X32-NEXT: lock cmpxchg8b (%esi)
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; X32-NEXT: movl %eax, %ebx
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; X32-NEXT: movl %edx, %ecx
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; X32-NEXT: notl %ecx
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; X32-NEXT: notl %ebx
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; X32-NEXT: movl (%esi), %eax
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; X32-NEXT: movl 4(%esi), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB61_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b (%esi)
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; X32-NEXT: jne .LBB61_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: popl %esi
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: popl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 4
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; X32-NEXT: retl
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; We do not check X86-32 as it cannot do 'notq'.
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%1 = load atomic i64, i64* %p acquire, align 8
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%2 = xor i64 %1, -1
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @not_32_seq_cst(i32* %p) {
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; X64-LABEL: not_32_seq_cst:
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; X64: # %bb.0:
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: notl %eax
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; X64-NEXT: xchgl %eax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: not_32_seq_cst:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: notl %ecx
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; X32-NEXT: xchgl %ecx, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i32, i32* %p monotonic, align 4
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%2 = xor i32 %1, -1
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- NEG -----
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define void @neg_8(i8* %p) {
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; X64-LABEL: neg_8:
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; X64: # %bb.0:
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; X64-NEXT: movb (%rdi), %al
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; X64-NEXT: negb %al
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; X64-NEXT: movb %al, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: neg_8:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movb (%eax), %cl
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; X32-NEXT: negb %cl
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; X32-NEXT: movb %cl, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i8, i8* %p seq_cst, align 1
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%2 = sub i8 0, %1
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store atomic i8 %2, i8* %p release, align 1
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ret void
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}
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define void @neg_16(i16* %p) {
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; Currently the transformation is neg done on 16 bit accesses, as the backend
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; treat 16 bit arithmetic as expensive on X86/X86_64.
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; X64-LABEL: neg_16:
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; X64: # %bb.0:
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; X64-NEXT: movw (%rdi), %ax
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; X64-NEXT: negl %eax
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; X64-NEXT: movw %ax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: neg_16:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movw (%eax), %cx
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; X32-NEXT: negl %ecx
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; X32-NEXT: movw %cx, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i16, i16* %p acquire, align 2
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%2 = sub i16 0, %1
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store atomic i16 %2, i16* %p release, align 2
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ret void
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}
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define void @neg_32(i32* %p) {
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; X64-LABEL: neg_32:
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; X64: # %bb.0:
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: movl %eax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: neg_32:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: negl %ecx
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; X32-NEXT: movl %ecx, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i32, i32* %p acquire, align 4
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%2 = sub i32 0, %1
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store atomic i32 %2, i32* %p monotonic, align 4
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ret void
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}
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define void @neg_64(i64* %p) {
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; X64-LABEL: neg_64:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: negq %rax
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; X64-NEXT: movq %rax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: neg_64:
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; X32: # %bb.0:
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; X32-NEXT: pushl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: pushl %edi
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; X32-NEXT: .cfi_def_cfa_offset 12
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; X32-NEXT: pushl %esi
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; X32-NEXT: .cfi_def_cfa_offset 16
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; X32-NEXT: .cfi_offset %esi, -16
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; X32-NEXT: .cfi_offset %edi, -12
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; X32-NEXT: .cfi_offset %ebx, -8
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: xorl %esi, %esi
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: xorl %ecx, %ecx
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; X32-NEXT: xorl %ebx, %ebx
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; X32-NEXT: lock cmpxchg8b (%edi)
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; X32-NEXT: movl %eax, %ebx
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; X32-NEXT: negl %ebx
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; X32-NEXT: sbbl %edx, %esi
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; X32-NEXT: movl (%edi), %eax
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; X32-NEXT: movl 4(%edi), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB66_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: movl %esi, %ecx
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; X32-NEXT: lock cmpxchg8b (%edi)
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; X32-NEXT: jne .LBB66_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: popl %esi
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; X32-NEXT: .cfi_def_cfa_offset 12
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; X32-NEXT: popl %edi
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: popl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 4
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; X32-NEXT: retl
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; We do neg check X86-32 as it canneg do 'negq'.
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%1 = load atomic i64, i64* %p acquire, align 8
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%2 = sub i64 0, %1
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store atomic i64 %2, i64* %p release, align 8
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ret void
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}
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define void @neg_32_seq_cst(i32* %p) {
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; X64-LABEL: neg_32_seq_cst:
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; X64: # %bb.0:
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: xchgl %eax, (%rdi)
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; X64-NEXT: retq
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;
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; X32-LABEL: neg_32_seq_cst:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: movl (%eax), %ecx
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; X32-NEXT: negl %ecx
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; X32-NEXT: xchgl %ecx, (%eax)
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; X32-NEXT: retl
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%1 = load atomic i32, i32* %p monotonic, align 4
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%2 = sub i32 0, %1
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store atomic i32 %2, i32* %p seq_cst, align 4
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ret void
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}
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; ----- FADD -----
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define void @fadd_32r(float* %loc, float %val) {
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@ -1574,10 +1838,10 @@ define void @fadd_64r(double* %loc, double %val) {
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; X32-NEXT: movl (%esi), %eax
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; X32-NEXT: movl 4(%esi), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB59_1: # %atomicrmw.start
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; X32-NEXT: .LBB69_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b (%esi)
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; X32-NEXT: jne .LBB59_1
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; X32-NEXT: jne .LBB69_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: leal -8(%ebp), %esp
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; X32-NEXT: popl %esi
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@ -1664,10 +1928,10 @@ define void @fadd_64g() {
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; X32-NEXT: movl glob64+4, %edx
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; X32-NEXT: movl glob64, %eax
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB61_1: # %atomicrmw.start
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; X32-NEXT: .LBB71_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b glob64
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; X32-NEXT: jne .LBB61_1
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; X32-NEXT: jne .LBB71_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: leal -4(%ebp), %esp
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; X32-NEXT: popl %ebx
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@ -1751,10 +2015,10 @@ define void @fadd_64imm() {
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; X32-NEXT: movl -559038737, %eax
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; X32-NEXT: movl -559038733, %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB63_1: # %atomicrmw.start
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; X32-NEXT: .LBB73_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b -559038737
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; X32-NEXT: jne .LBB63_1
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; X32-NEXT: jne .LBB73_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: leal -4(%ebp), %esp
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; X32-NEXT: popl %ebx
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@ -1838,10 +2102,10 @@ define void @fadd_64stack() {
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; X32-NEXT: movl (%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB65_1: # %atomicrmw.start
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; X32-NEXT: .LBB75_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b (%esp)
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; X32-NEXT: jne .LBB65_1
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; X32-NEXT: jne .LBB75_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: leal -4(%ebp), %esp
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; X32-NEXT: popl %ebx
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@ -1898,10 +2162,10 @@ define void @fadd_array(i64* %arg, double %arg1, i64 %arg2) {
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; X32-NEXT: movl (%edi,%esi,8), %eax
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; X32-NEXT: movl 4(%edi,%esi,8), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB66_1: # %atomicrmw.start
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; X32-NEXT: .LBB76_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: lock cmpxchg8b (%edi,%esi,8)
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; X32-NEXT: jne .LBB66_1
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; X32-NEXT: jne .LBB76_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: leal -12(%ebp), %esp
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; X32-NEXT: popl %esi
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