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Be less specific about register allocation ordering. 

llvm-svn: 134308
This commit is contained in:
Eric Christopher 2011-07-02 04:06:41 +00:00
parent 25a404eb81
commit 2eca9d5ddf
1 changed files with 2 additions and 2 deletions
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4
llvm/test/CodeGen/X86/atomic-or.ll
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@ -11,7 +11,7 @@ entry:
; CHECK: t1:
; CHECK: movl $2147483648, %eax
; CHECK: lock
; CHECK-NEXT: orq %rax, (%rdi)
; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
%0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
ret void
@ -26,7 +26,7 @@ entry:
; CHECK: t2:
; CHECK-NOT: movl
; CHECK: lock
; CHECK-NEXT: orq $2147483644, (%rdi)
; CHECK-NEXT: orq $2147483644, (%r{{.*}})
%0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644)
call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
ret void