[DAGCombine][X86][AArch64][NFC] Add tests for shift-by-signext
llvm-svn: 373014
This commit is contained in:
Roman Lebedev
parent
86b40b0bbf
commit
3a5ca1c8b5
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
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; If we have a shift by sign-extended value, we can replace sign-extension
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; with zero-extension.
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define i32 @t0_shl(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t0_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsl w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t1_lshr(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t1_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsr w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = lshr i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t2_ashr(i32 %x, i8 %shamt) nounwind {
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; CHECK-LABEL: t2_ashr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: asr w0, w0, w8
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = ashr i32 %x, %shamt_wide
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ret i32 %r
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}
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define <4 x i32> @t3_vec_shl(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t3_vec_shl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = shl <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t4_vec_lshr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t4_vec_lshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = lshr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t5_vec_ashr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t5_vec_ashr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #24
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; CHECK-NEXT: sshr v1.4s, v1.4s, #24
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; CHECK-NEXT: neg v1.4s, v1.4s
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; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = ashr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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; This is not valid for funnel shifts
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declare i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
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declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
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define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {
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; CHECK-LABEL: n6_fshl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w2, #0x1f
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; CHECK-NEXT: neg w9, w9
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; CHECK-NEXT: lsl w8, w0, w2
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; CHECK-NEXT: lsr w9, w1, w9
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; CHECK-NEXT: orr w8, w8, w9
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; CHECK-NEXT: tst w2, #0x1f
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; CHECK-NEXT: csel w0, w0, w8, eq
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) nounwind {
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; CHECK-LABEL: n7_fshr:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w2, #0x1f
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; CHECK-NEXT: neg w9, w9
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; CHECK-NEXT: lsr w8, w1, w2
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; CHECK-NEXT: lsl w9, w0, w9
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; CHECK-NEXT: orr w8, w9, w8
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; CHECK-NEXT: tst w2, #0x1f
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; CHECK-NEXT: csel w0, w1, w8, eq
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n8_extrause(i32 %x, i8 %shamt, i32* %shamt_wide_store) nounwind {
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; CHECK-LABEL: n8_extrause:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sxtb w8, w1
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; CHECK-NEXT: lsl w0, w0, w8
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; CHECK-NEXT: str w8, [x2]
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; CHECK-NEXT: ret
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%shamt_wide = sext i8 %shamt to i32
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store i32 %shamt_wide, i32* %shamt_wide_store, align 4
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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@ -0,0 +1,148 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+bmi2,+sse,+sse2,+avx,+avx2 | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2,+sse,+sse2,+avx,+avx2 | FileCheck %s --check-prefixes=CHECK,X64
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; If we have a shift by sign-extended value, we can replace sign-extension
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; with zero-extension.
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define i32 @t0_shl(i32 %x, i8 %shamt) nounwind {
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; X86-LABEL: t0_shl:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t0_shl:
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; X64: # %bb.0:
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; X64-NEXT: shlxl %esi, %edi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t1_lshr(i32 %x, i8 %shamt) nounwind {
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; X86-LABEL: t1_lshr:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: shrxl %eax, {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t1_lshr:
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; X64: # %bb.0:
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; X64-NEXT: shrxl %esi, %edi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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%r = lshr i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t2_ashr(i32 %x, i8 %shamt) nounwind {
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; X86-LABEL: t2_ashr:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-NEXT: sarxl %eax, {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: t2_ashr:
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; X64: # %bb.0:
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; X64-NEXT: sarxl %esi, %edi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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%r = ashr i32 %x, %shamt_wide
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ret i32 %r
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}
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define <4 x i32> @t3_vec_shl(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t3_vec_shl:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpmovsxbd %xmm1, %xmm1
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; CHECK-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = shl <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t4_vec_lshr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t4_vec_lshr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpmovsxbd %xmm1, %xmm1
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; CHECK-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = lshr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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define <4 x i32> @t5_vec_ashr(<4 x i32> %x, <4 x i8> %shamt) nounwind {
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; CHECK-LABEL: t5_vec_ashr:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vpmovsxbd %xmm1, %xmm1
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; CHECK-NEXT: vpsravd %xmm1, %xmm0, %xmm0
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; CHECK-NEXT: ret{{[l|q]}}
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%shamt_wide = sext <4 x i8> %shamt to <4 x i32>
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%r = ashr <4 x i32> %x, %shamt_wide
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ret <4 x i32> %r
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}
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; This is not valid for funnel shifts
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declare i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)
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declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)
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define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {
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; X86-LABEL: n6_fshl:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shldl %cl, %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n6_fshl:
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; X64: # %bb.0:
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; X64-NEXT: movl %edx, %ecx
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shldl %cl, %esi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) nounwind {
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; X86-LABEL: n7_fshr:
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; X86: # %bb.0:
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; X86-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shrdl %cl, %edx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n7_fshr:
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; X64: # %bb.0:
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; X64-NEXT: movl %edx, %ecx
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; X64-NEXT: movl %esi, %eax
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shrdl %cl, %edi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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%r = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %shamt_wide)
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ret i32 %r
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}
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define i32 @n8_extrause(i32 %x, i8 %shamt, i32* %shamt_wide_store) nounwind {
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; X86-LABEL: n8_extrause:
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; X86: # %bb.0:
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; X86-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %eax, (%ecx)
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; X86-NEXT: shlxl %eax, {{[0-9]+}}(%esp), %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: n8_extrause:
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; X64: # %bb.0:
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; X64-NEXT: movsbl %sil, %eax
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; X64-NEXT: movl %eax, (%rdx)
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; X64-NEXT: shlxl %eax, %edi, %eax
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; X64-NEXT: retq
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%shamt_wide = sext i8 %shamt to i32
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store i32 %shamt_wide, i32* %shamt_wide_store, align 4
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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