OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

A better fix for my previous patch, MOVZQI2PQIrr just requires SSE2. 

llvm-svn: 49986
This commit is contained in:
Chris Lattner 2008-04-20 05:52:46 +00:00
parent a124f1e219
commit 470ab00c76
2 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -2312,7 +2312,7 @@ def : Pat<(v2f64 (vector_shuffle immAllZerosV_bc,
(v2f64 (scalar_to_vector
(f64 (bitconvert GR64:$src)))),
MOVL_shuffle_mask)),
(MOVZQI2PQIrr GR64:$src)>, Requires<[HasSSE3]>;
(MOVZQI2PQIrr GR64:$src)>, Requires<[HasSSE2]>;
let AddedComplexity = 20 in {

4
llvm/test/CodeGen/X86/vec_shuffle-17.ll
View File

@ -1,5 +1,5 @@
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse3 | grep {movd.*%rdi, %xmm0}
; RUN: llvm-as < %s | llc -march=x86-64 -mattr=+sse3 | not grep xor
; RUN: llvm-as < %s | llc -march=x86-64 | grep {movd.*%rdi, %xmm0}
; RUN: llvm-as < %s | llc -march=x86-64 | not grep xor
; PR2108
define <2 x i64> @doload64(i64 %x) nounwind {