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Neon does not actually have VLD{234}.64 instructions. 

These operations will have to be synthesized from other instructions.

llvm-svn: 78263
This commit is contained in:
Bob Wilson 2009-08-06 00:24:27 +00:00
parent 13c5a27c9a
commit 488db94e7b
3 changed files with 0 additions and 9 deletions
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3
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1317,7 +1317,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD2d16; break; case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32: case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break; case MVT::v2i32: Opc = ARM::VLD2d32; break;
case MVT::v1i64: Opc = ARM::VLD2d64; break;
} }
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3); return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
@ -1335,7 +1334,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD3d16; break; case MVT::v4i16: Opc = ARM::VLD3d16; break;
case MVT::v2f32: case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD3d32; break; case MVT::v2i32: Opc = ARM::VLD3d32; break;
case MVT::v1i64: Opc = ARM::VLD3d64; break;
} }
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3); return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
@ -1353,7 +1351,6 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD4d16; break; case MVT::v4i16: Opc = ARM::VLD4d16; break;
case MVT::v2f32: case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD4d32; break; case MVT::v2i32: Opc = ARM::VLD4d32; break;
case MVT::v1i64: Opc = ARM::VLD4d64; break;
} }
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
std::vector<MVT> ResTys(4, VT); std::vector<MVT> ResTys(4, VT);

3
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -196,7 +196,6 @@ class VLD2D<string OpcodeStr>
def VLD2d8 : VLD2D<"vld2.8">; def VLD2d8 : VLD2D<"vld2.8">;
def VLD2d16 : VLD2D<"vld2.16">; def VLD2d16 : VLD2D<"vld2.16">;
def VLD2d32 : VLD2D<"vld2.32">; def VLD2d32 : VLD2D<"vld2.32">;
def VLD2d64 : VLD2D<"vld2.64">;
// VLD3 : Vector Load (multiple 3-element structures) // VLD3 : Vector Load (multiple 3-element structures)
class VLD3D<string OpcodeStr> class VLD3D<string OpcodeStr>
@ -206,7 +205,6 @@ class VLD3D<string OpcodeStr>
def VLD3d8 : VLD3D<"vld3.8">; def VLD3d8 : VLD3D<"vld3.8">;
def VLD3d16 : VLD3D<"vld3.16">; def VLD3d16 : VLD3D<"vld3.16">;
def VLD3d32 : VLD3D<"vld3.32">; def VLD3d32 : VLD3D<"vld3.32">;
def VLD3d64 : VLD3D<"vld3.64">;
// VLD4 : Vector Load (multiple 4-element structures) // VLD4 : Vector Load (multiple 4-element structures)
class VLD4D<string OpcodeStr> class VLD4D<string OpcodeStr>
@ -217,7 +215,6 @@ class VLD4D<string OpcodeStr>
def VLD4d8 : VLD4D<"vld4.8">; def VLD4d8 : VLD4D<"vld4.8">;
def VLD4d16 : VLD4D<"vld4.16">; def VLD4d16 : VLD4D<"vld4.16">;
def VLD4d32 : VLD4D<"vld4.32">; def VLD4d32 : VLD4D<"vld4.32">;
def VLD4d64 : VLD4D<"vld4.64">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

3
llvm/lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -45,7 +45,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD2d8: case ARM::VLD2d8:
case ARM::VLD2d16: case ARM::VLD2d16:
case ARM::VLD2d32: case ARM::VLD2d32:
case ARM::VLD2d64:
FirstOpnd = 0; FirstOpnd = 0;
NumRegs = 2; NumRegs = 2;
return true; return true;
@ -53,7 +52,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD3d8: case ARM::VLD3d8:
case ARM::VLD3d16: case ARM::VLD3d16:
case ARM::VLD3d32: case ARM::VLD3d32:
case ARM::VLD3d64:
FirstOpnd = 0; FirstOpnd = 0;
NumRegs = 3; NumRegs = 3;
return true; return true;
@ -61,7 +59,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd,
case ARM::VLD4d8: case ARM::VLD4d8:
case ARM::VLD4d16: case ARM::VLD4d16:
case ARM::VLD4d32: case ARM::VLD4d32:
case ARM::VLD4d64:
FirstOpnd = 0; FirstOpnd = 0;
NumRegs = 4; NumRegs = 4;
return true; return true;