parent
1992e8f38e
commit
48e2eb0b27
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@ -840,13 +840,10 @@ bool AArch64InstructionSelector::selectVectorSHL(
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return false;
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return false;
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unsigned Opc = 0;
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unsigned Opc = 0;
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const TargetRegisterClass *RC = nullptr;
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if (Ty == LLT::vector(4, 32)) {
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if (Ty == LLT::vector(4, 32)) {
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Opc = AArch64::USHLv4i32;
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Opc = AArch64::USHLv4i32;
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RC = &AArch64::FPR128RegClass;
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} else if (Ty == LLT::vector(2, 32)) {
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} else if (Ty == LLT::vector(2, 32)) {
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Opc = AArch64::USHLv2i32;
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Opc = AArch64::USHLv2i32;
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RC = &AArch64::FPR64RegClass;
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} else {
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} else {
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LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
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LLVM_DEBUG(dbgs() << "Unhandled G_SHL type");
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return false;
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return false;
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