[X86] Rename funnel-shift X32 check prefixes to X86
We try to use X32 for gnux32 triple checks only
This commit is contained in:
Simon Pilgrim
parent
b2c9b7d82a
commit
55aecfb936
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@ -1,6 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s --check-prefixes=ANY,X32-SSE2
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=ANY,X64-AVX2
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; RUN: llc < %s -mtriple=i686-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,X86-SSE2
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; RUN: llc < %s -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,X64-AVX2
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declare i8 @llvm.fshl.i8(i8, i8, i8)
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declare i16 @llvm.fshl.i16(i16, i16, i16)
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@ -17,11 +17,11 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
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; When first 2 operands match, it's a rotate.
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define i8 @rotl_i8_const_shift(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotl_i8_const_shift:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rolb $3, %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i8_const_shift:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rolb $3, %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i8_const_shift:
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; X64-AVX2: # %bb.0:
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@ -34,11 +34,11 @@ define i8 @rotl_i8_const_shift(i8 %x) nounwind {
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}
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define i8 @rotl_i8_const_shift1(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotl_i8_const_shift1:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rolb %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i8_const_shift1:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rolb %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i8_const_shift1:
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; X64-AVX2: # %bb.0:
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@ -51,11 +51,11 @@ define i8 @rotl_i8_const_shift1(i8 %x) nounwind {
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}
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define i8 @rotl_i8_const_shift7(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotl_i8_const_shift7:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rorb %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i8_const_shift7:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rorb %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i8_const_shift7:
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; X64-AVX2: # %bb.0:
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@ -68,14 +68,14 @@ define i8 @rotl_i8_const_shift7(i8 %x) nounwind {
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}
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define i64 @rotl_i64_const_shift(i64 %x) nounwind {
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; X32-SSE2-LABEL: rotl_i64_const_shift:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-SSE2-NEXT: movl %ecx, %eax
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; X32-SSE2-NEXT: shldl $3, %edx, %eax
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; X32-SSE2-NEXT: shldl $3, %ecx, %edx
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i64_const_shift:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-SSE2-NEXT: movl %ecx, %eax
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; X86-SSE2-NEXT: shldl $3, %edx, %eax
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; X86-SSE2-NEXT: shldl $3, %ecx, %edx
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i64_const_shift:
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; X64-AVX2: # %bb.0:
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@ -87,12 +87,12 @@ define i64 @rotl_i64_const_shift(i64 %x) nounwind {
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}
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define i16 @rotl_i16(i16 %x, i16 %z) nounwind {
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; X32-SSE2-LABEL: rotl_i16:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-SSE2-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: rolw %cl, %ax
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i16:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-SSE2-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: rolw %cl, %ax
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i16:
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; X64-AVX2: # %bb.0:
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@ -107,12 +107,12 @@ define i16 @rotl_i16(i16 %x, i16 %z) nounwind {
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}
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define i32 @rotl_i32(i32 %x, i32 %z) nounwind {
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; X32-SSE2-LABEL: rotl_i32:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: roll %cl, %eax
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_i32:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: roll %cl, %eax
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_i32:
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; X64-AVX2: # %bb.0:
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@ -128,24 +128,24 @@ define i32 @rotl_i32(i32 %x, i32 %z) nounwind {
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; Vector rotate.
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define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
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; X32-SSE2-LABEL: rotl_v4i32:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X32-SSE2-NEXT: pslld $23, %xmm1
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; X32-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X32-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X32-SSE2-NEXT: por %xmm3, %xmm0
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_v4i32:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X86-SSE2-NEXT: pslld $23, %xmm1
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; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
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; X86-SSE2-NEXT: cvttps2dq %xmm1, %xmm1
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
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; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
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; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
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; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
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; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
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; X86-SSE2-NEXT: por %xmm3, %xmm0
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_v4i32:
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; X64-AVX2: # %bb.0:
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@ -164,13 +164,13 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
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; Vector rotate by constant splat amount.
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define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) nounwind {
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; X32-SSE2-LABEL: rotl_v4i32_const_shift:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movdqa %xmm0, %xmm1
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; X32-SSE2-NEXT: psrld $29, %xmm1
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; X32-SSE2-NEXT: pslld $3, %xmm0
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; X32-SSE2-NEXT: por %xmm1, %xmm0
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotl_v4i32_const_shift:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
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; X86-SSE2-NEXT: psrld $29, %xmm1
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; X86-SSE2-NEXT: pslld $3, %xmm0
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; X86-SSE2-NEXT: por %xmm1, %xmm0
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotl_v4i32_const_shift:
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; X64-AVX2: # %bb.0:
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@ -185,11 +185,11 @@ define <4 x i32> @rotl_v4i32_const_shift(<4 x i32> %x) nounwind {
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; Repeat everything for funnel shift right.
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define i8 @rotr_i8_const_shift(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotr_i8_const_shift:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rorb $3, %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i8_const_shift:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rorb $3, %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotr_i8_const_shift:
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; X64-AVX2: # %bb.0:
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@ -202,11 +202,11 @@ define i8 @rotr_i8_const_shift(i8 %x) nounwind {
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}
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define i8 @rotr_i8_const_shift1(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotr_i8_const_shift1:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rorb %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i8_const_shift1:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rorb %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotr_i8_const_shift1:
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; X64-AVX2: # %bb.0:
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@ -219,11 +219,11 @@ define i8 @rotr_i8_const_shift1(i8 %x) nounwind {
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}
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define i8 @rotr_i8_const_shift7(i8 %x) nounwind {
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; X32-SSE2-LABEL: rotr_i8_const_shift7:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-SSE2-NEXT: rolb %al
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i8_const_shift7:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %al
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; X86-SSE2-NEXT: rolb %al
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotr_i8_const_shift7:
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; X64-AVX2: # %bb.0:
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@ -236,11 +236,11 @@ define i8 @rotr_i8_const_shift7(i8 %x) nounwind {
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}
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define i32 @rotr_i32_const_shift(i32 %x) nounwind {
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; X32-SSE2-LABEL: rotr_i32_const_shift:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: rorl $3, %eax
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i32_const_shift:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: rorl $3, %eax
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotr_i32_const_shift:
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; X64-AVX2: # %bb.0:
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@ -254,12 +254,12 @@ define i32 @rotr_i32_const_shift(i32 %x) nounwind {
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; When first 2 operands match, it's a rotate (by variable amount).
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define i16 @rotr_i16(i16 %x, i16 %z) nounwind {
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; X32-SSE2-LABEL: rotr_i16:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X32-SSE2-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: rorw %cl, %ax
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i16:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: movb {{[0-9]+}}(%esp), %cl
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; X86-SSE2-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-SSE2-NEXT: rorw %cl, %ax
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; X86-SSE2-NEXT: retl
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;
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; X64-AVX2-LABEL: rotr_i16:
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; X64-AVX2: # %bb.0:
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@ -274,22 +274,22 @@ define i16 @rotr_i16(i16 %x, i16 %z) nounwind {
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}
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define i64 @rotr_i64(i64 %x, i64 %z) nounwind {
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; X32-SSE2-LABEL: rotr_i64:
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; X32-SSE2: # %bb.0:
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; X32-SSE2-NEXT: pushl %esi
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE2-NEXT: testb $32, %cl
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; X32-SSE2-NEXT: movl %eax, %edx
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; X32-SSE2-NEXT: cmovel %esi, %edx
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; X32-SSE2-NEXT: cmovel %eax, %esi
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; X32-SSE2-NEXT: movl %esi, %eax
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; X32-SSE2-NEXT: shrdl %cl, %edx, %eax
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; X32-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
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; X32-SSE2-NEXT: shrdl %cl, %esi, %edx
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; X32-SSE2-NEXT: popl %esi
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; X32-SSE2-NEXT: retl
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; X86-SSE2-LABEL: rotr_i64:
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; X86-SSE2: # %bb.0:
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; X86-SSE2-NEXT: pushl %esi
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %esi
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-SSE2-NEXT: testb $32, %cl
|
||||
; X86-SSE2-NEXT: movl %eax, %edx
|
||||
; X86-SSE2-NEXT: cmovel %esi, %edx
|
||||
; X86-SSE2-NEXT: cmovel %eax, %esi
|
||||
; X86-SSE2-NEXT: movl %esi, %eax
|
||||
; X86-SSE2-NEXT: shrdl %cl, %edx, %eax
|
||||
; X86-SSE2-NEXT: # kill: def $cl killed $cl killed $ecx
|
||||
; X86-SSE2-NEXT: shrdl %cl, %esi, %edx
|
||||
; X86-SSE2-NEXT: popl %esi
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: rotr_i64:
|
||||
; X64-AVX2: # %bb.0:
|
||||
|
|
@ -305,26 +305,26 @@ define i64 @rotr_i64(i64 %x, i64 %z) nounwind {
|
|||
; Vector rotate.
|
||||
|
||||
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
|
||||
; X32-SSE2-LABEL: rotr_v4i32:
|
||||
; X32-SSE2: # %bb.0:
|
||||
; X32-SSE2-NEXT: pxor %xmm2, %xmm2
|
||||
; X32-SSE2-NEXT: psubd %xmm1, %xmm2
|
||||
; X32-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
|
||||
; X32-SSE2-NEXT: pslld $23, %xmm2
|
||||
; X32-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
|
||||
; X32-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
||||
; X32-SSE2-NEXT: pmuludq %xmm1, %xmm0
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; X32-SSE2-NEXT: pmuludq %xmm2, %xmm1
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
|
||||
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; X32-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
|
||||
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; X32-SSE2-NEXT: por %xmm3, %xmm0
|
||||
; X32-SSE2-NEXT: retl
|
||||
; X86-SSE2-LABEL: rotr_v4i32:
|
||||
; X86-SSE2: # %bb.0:
|
||||
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
|
||||
; X86-SSE2-NEXT: psubd %xmm1, %xmm2
|
||||
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
|
||||
; X86-SSE2-NEXT: pslld $23, %xmm2
|
||||
; X86-SSE2-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
|
||||
; X86-SSE2-NEXT: cvttps2dq %xmm2, %xmm1
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
||||
; X86-SSE2-NEXT: pmuludq %xmm1, %xmm0
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,3,2,3]
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; X86-SSE2-NEXT: pmuludq %xmm2, %xmm1
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,3,2,3]
|
||||
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; X86-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
|
||||
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; X86-SSE2-NEXT: por %xmm3, %xmm0
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: rotr_v4i32:
|
||||
; X64-AVX2: # %bb.0:
|
||||
|
|
@ -345,13 +345,13 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
|
|||
; Vector rotate by constant splat amount.
|
||||
|
||||
define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) nounwind {
|
||||
; X32-SSE2-LABEL: rotr_v4i32_const_shift:
|
||||
; X32-SSE2: # %bb.0:
|
||||
; X32-SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; X32-SSE2-NEXT: psrld $3, %xmm1
|
||||
; X32-SSE2-NEXT: pslld $29, %xmm0
|
||||
; X32-SSE2-NEXT: por %xmm1, %xmm0
|
||||
; X32-SSE2-NEXT: retl
|
||||
; X86-SSE2-LABEL: rotr_v4i32_const_shift:
|
||||
; X86-SSE2: # %bb.0:
|
||||
; X86-SSE2-NEXT: movdqa %xmm0, %xmm1
|
||||
; X86-SSE2-NEXT: psrld $3, %xmm1
|
||||
; X86-SSE2-NEXT: pslld $29, %xmm0
|
||||
; X86-SSE2-NEXT: por %xmm1, %xmm0
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: rotr_v4i32_const_shift:
|
||||
; X64-AVX2: # %bb.0:
|
||||
|
|
@ -364,10 +364,10 @@ define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) nounwind {
|
|||
}
|
||||
|
||||
define i32 @rotl_i32_shift_by_bitwidth(i32 %x) nounwind {
|
||||
; X32-SSE2-LABEL: rotl_i32_shift_by_bitwidth:
|
||||
; X32-SSE2: # %bb.0:
|
||||
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-SSE2-NEXT: retl
|
||||
; X86-SSE2-LABEL: rotl_i32_shift_by_bitwidth:
|
||||
; X86-SSE2: # %bb.0:
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: rotl_i32_shift_by_bitwidth:
|
||||
; X64-AVX2: # %bb.0:
|
||||
|
|
@ -378,10 +378,10 @@ define i32 @rotl_i32_shift_by_bitwidth(i32 %x) nounwind {
|
|||
}
|
||||
|
||||
define i32 @rotr_i32_shift_by_bitwidth(i32 %x) nounwind {
|
||||
; X32-SSE2-LABEL: rotr_i32_shift_by_bitwidth:
|
||||
; X32-SSE2: # %bb.0:
|
||||
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-SSE2-NEXT: retl
|
||||
; X86-SSE2-LABEL: rotr_i32_shift_by_bitwidth:
|
||||
; X86-SSE2: # %bb.0:
|
||||
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X86-SSE2-NEXT: retl
|
||||
;
|
||||
; X64-AVX2-LABEL: rotr_i32_shift_by_bitwidth:
|
||||
; X64-AVX2: # %bb.0:
|
||||
|
|
@ -392,17 +392,17 @@ define i32 @rotr_i32_shift_by_bitwidth(i32 %x) nounwind {
|
|||
}
|
||||
|
||||
define <4 x i32> @rotl_v4i32_shift_by_bitwidth(<4 x i32> %x) nounwind {
|
||||
; ANY-LABEL: rotl_v4i32_shift_by_bitwidth:
|
||||
; ANY: # %bb.0:
|
||||
; ANY-NEXT: ret{{[l|q]}}
|
||||
; CHECK-LABEL: rotl_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
||||
define <4 x i32> @rotr_v4i32_shift_by_bitwidth(<4 x i32> %x) nounwind {
|
||||
; ANY-LABEL: rotr_v4i32_shift_by_bitwidth:
|
||||
; ANY: # %bb.0:
|
||||
; ANY-NEXT: ret{{[l|q]}}
|
||||
; CHECK-LABEL: rotr_v4i32_shift_by_bitwidth:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
|
||||
ret <4 x i32> %f
|
||||
}
|
||||
|
|
@ -416,10 +416,10 @@ declare i7 @llvm.fshr.i7(i7, i7, i7)
|
|||
; Try an oversized shift to test modulo functionality.
|
||||
|
||||
define i7 @fshl_i7() {
|
||||
; ANY-LABEL: fshl_i7:
|
||||
; ANY: # %bb.0:
|
||||
; ANY-NEXT: movb $67, %al
|
||||
; ANY-NEXT: ret{{[l|q]}}
|
||||
; CHECK-LABEL: fshl_i7:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movb $67, %al
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
%f = call i7 @llvm.fshl.i7(i7 112, i7 112, i7 9)
|
||||
ret i7 %f
|
||||
}
|
||||
|
|
@ -428,10 +428,10 @@ define i7 @fshl_i7() {
|
|||
; Try an oversized shift to test modulo functionality.
|
||||
|
||||
define i7 @fshr_i7() {
|
||||
; ANY-LABEL: fshr_i7:
|
||||
; ANY: # %bb.0:
|
||||
; ANY-NEXT: movb $60, %al
|
||||
; ANY-NEXT: ret{{[l|q]}}
|
||||
; CHECK-LABEL: fshr_i7:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movb $60, %al
|
||||
; CHECK-NEXT: ret{{[l|q]}}
|
||||
%f = call i7 @llvm.fshr.i7(i7 113, i7 113, i7 16)
|
||||
ret i7 %f
|
||||
}
|
||||
|
|
|
|||
File diff suppressed because it is too large
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Reference in New Issue