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Revert the remaining part of r139528. According to PR10907 the bug seems 

to be in the VSELECT operands order, so I'll leave the fix for Nadav.

llvm-svn: 139624
This commit is contained in:
Bruno Cardoso Lopes 2011-09-13 19:33:00 +00:00
parent 52202fbf2d
commit 56d9b51caf
1 changed files with 5 additions and 5 deletions
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10
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -8483,20 +8483,20 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const {
if (SSECC == 8) { if (SSECC == 8) {
if (SetCCOpcode == ISD::SETUEQ) { if (SetCCOpcode == ISD::SETUEQ) {
SDValue UNORD, EQ; SDValue UNORD, EQ;
UNORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(3, MVT::i8)); UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
EQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(0, MVT::i8)); EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ);
} }
else if (SetCCOpcode == ISD::SETONE) { else if (SetCCOpcode == ISD::SETONE) {
SDValue ORD, NEQ; SDValue ORD, NEQ;
ORD = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(7, MVT::i8)); ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8));
NEQ = DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(4, MVT::i8)); NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8));
return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ);
} }
llvm_unreachable("Illegal FP comparison"); llvm_unreachable("Illegal FP comparison");
} }
// Handle all other FP comparisons here. // Handle all other FP comparisons here.
return DAG.getNode(Opc, dl, VT, Op1, Op0, DAG.getConstant(SSECC, MVT::i8)); return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
} }
// Break 256-bit integer vector compare into smaller ones. // Break 256-bit integer vector compare into smaller ones.