[RISCV] Add an extra vsetvli insertion test
This test starts failing with the changes in D125021.
This commit is contained in:
Fraser Cormack
parent
37ba1b9d1a
commit
588155aaa7
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@ -125,6 +125,10 @@
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ret void
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}
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define void @if_in_loop() {
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ret void
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}
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; Function Attrs: nofree nosync nounwind readnone willreturn
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declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>)
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@ -822,3 +826,105 @@ body: |
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PseudoRET
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...
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---
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name: if_in_loop
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: if_in_loop
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $x10, $x11, $x12, $x13, $x14, $x15
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %dst:gpr = COPY $x10
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; CHECK-NEXT: %src:gpr = COPY $x11
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: %tc:gpr = COPY $x13
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x14
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x15
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; CHECK-NEXT: %vlenb:gpr = PseudoReadVLENB
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; CHECK-NEXT: %inc:gpr = SRLI killed %vlenb, 3
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; CHECK-NEXT: dead %21:gpr = PseudoVSETVLIX0 $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 -1, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %11, %bb.3
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; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[PHI]]
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; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
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; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], killed [[ADD]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
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; CHECK-NEXT: BEQ killed [[PseudoVCPOP_M_B1_]], [[COPY4]], %bb.3
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; CHECK-NEXT: PseudoBR %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.3(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[PHI]]
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; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 69 /* e8, mf8, ta, mu */, implicit-def $vl, implicit-def $vtype, implicit $vl
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; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 killed [[ADD1]], -1, 3 /* e8 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[PHI]]
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; CHECK-NEXT: PseudoVSE8_V_MF8 killed [[PseudoVADD_VI_MF8_]], killed [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PHI]], %inc
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; CHECK-NEXT: BLTU [[ADD3]], %tc, %bb.1
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; CHECK-NEXT: PseudoBR %bb.4
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: PseudoRET
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bb.0:
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successors: %bb.1(0x80000000)
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liveins: $x10, $x11, $x12, $x13, $x14, $x15
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%dst:gpr = COPY $x10
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%src:gpr = COPY $x11
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%48:gpr = COPY $x12
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%tc:gpr = COPY $x13
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%11:gpr = COPY $x14
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%12:gpr = COPY $x15
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%vlenb:gpr = PseudoReadVLENB
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%inc:gpr = SRLI killed %vlenb, 3
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%10:vr = PseudoVID_V_M1 -1, 6
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%59:gpr = COPY $x0
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PseudoBR %bb.1
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bb.1:
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successors: %bb.2(0x40000000), %bb.3(0x40000000)
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%26:gpr = PHI %59, %bb.0, %28, %bb.3
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%61:gpr = ADD %12, %26
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%27:vr = PseudoVADD_VX_M1 %10, killed %61, -1, 6
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%62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6
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%63:gpr = PseudoVCPOP_M_B1 %62, -1, 0
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%64:gpr = COPY $x0
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BEQ killed %63, %64, %bb.3
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PseudoBR %bb.2
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bb.2:
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successors: %bb.3(0x80000000)
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%66:gpr = ADD %src, %26
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%67:vrnov0 = PseudoVLE8_V_MF8 killed %66, -1, 3
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%76:vrnov0 = PseudoVADD_VI_MF8 %67, 4, -1, 3
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%77:gpr = ADD %dst, %26
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PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3
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bb.3:
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successors: %bb.1(0x7c000000), %bb.4(0x04000000)
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%28:gpr = ADD %26, %inc
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BLTU %28, %tc, %bb.1
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PseudoBR %bb.4
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bb.4:
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PseudoRET
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...
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