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[X86] Remove isel checks for immediate size on floating point compare and xop compare instructions. NFCI 

If these checks fail we end up not selecting an instruction at all. So we are already relying on the immediate being checked upstream of isel. So doing the check in isel is just bloat to the isel table. Interestingly, we didn't check on the AVX512 version of the instructions anyway.

llvm-svn: 313724
This commit is contained in:
Craig Topper 2017-09-20 06:38:41 +00:00
parent 2e3bf37ec4
commit 5c7cd25f82
3 changed files with 26 additions and 36 deletions
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8
llvm/lib/Target/X86/X86InstrInfo.td
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@ -590,19 +590,11 @@ def SSECC : Operand<i8> {
let OperandType = "OPERAND_IMMEDIATE"; let OperandType = "OPERAND_IMMEDIATE";
} }
def i8immZExt3 : ImmLeaf<i8, [{
return Imm >= 0 && Imm < 8;
}]>;
def AVXCC : Operand<i8> { def AVXCC : Operand<i8> {
let PrintMethod = "printSSEAVXCC"; let PrintMethod = "printSSEAVXCC";
let OperandType = "OPERAND_IMMEDIATE"; let OperandType = "OPERAND_IMMEDIATE";
} }
def i8immZExt5 : ImmLeaf<i8, [{
return Imm >= 0 && Imm < 32;
}]>;
def AVX512ICC : Operand<i8> { def AVX512ICC : Operand<i8> {
let PrintMethod = "printSSEAVXCC"; let PrintMethod = "printSSEAVXCC";
let OperandType = "OPERAND_IMMEDIATE"; let OperandType = "OPERAND_IMMEDIATE";

50
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -2071,16 +2071,16 @@ let Predicates = [UseSSE2] in {
multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop, multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
Operand CC, SDNode OpNode, ValueType VT, Operand CC, SDNode OpNode, ValueType VT,
PatFrag ld_frag, string asm, string asm_alt, PatFrag ld_frag, string asm, string asm_alt,
OpndItins itins, ImmLeaf immLeaf> { OpndItins itins> {
let isCommutable = 1 in let isCommutable = 1 in
def rr : SIi8<0xC2, MRMSrcReg, def rr : SIi8<0xC2, MRMSrcReg,
(outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
[(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, immLeaf:$cc))], [(set RC:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
itins.rr>, Sched<[itins.Sched]>; itins.rr>, Sched<[itins.Sched]>;
def rm : SIi8<0xC2, MRMSrcMem, def rm : SIi8<0xC2, MRMSrcMem,
(outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
[(set RC:$dst, (OpNode (VT RC:$src1), [(set RC:$dst, (OpNode (VT RC:$src1),
(ld_frag addr:$src2), immLeaf:$cc))], (ld_frag addr:$src2), imm:$cc))],
itins.rm>, itins.rm>,
Sched<[itins.Sched.Folded, ReadAfterLd]>; Sched<[itins.Sched.Folded, ReadAfterLd]>;
@ -2101,41 +2101,41 @@ let ExeDomain = SSEPackedSingle in
defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32, defm VCMPSS : sse12_cmp_scalar<FR32, f32mem, AVXCC, X86cmps, f32, loadf32,
"cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSE_ALU_F32S, i8immZExt5>, XS, VEX_4V, VEX_LIG, VEX_WIG; SSE_ALU_F32S>, XS, VEX_4V, VEX_LIG, VEX_WIG;
let ExeDomain = SSEPackedDouble in let ExeDomain = SSEPackedDouble in
defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64, defm VCMPSD : sse12_cmp_scalar<FR64, f64mem, AVXCC, X86cmps, f64, loadf64,
"cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSE_ALU_F32S, i8immZExt5>, // same latency as 32 bit compare SSE_ALU_F32S>, // same latency as 32 bit compare
XD, VEX_4V, VEX_LIG, VEX_WIG; XD, VEX_4V, VEX_LIG, VEX_WIG;
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
let ExeDomain = SSEPackedSingle in let ExeDomain = SSEPackedSingle in
defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32, defm CMPSS : sse12_cmp_scalar<FR32, f32mem, SSECC, X86cmps, f32, loadf32,
"cmp${cc}ss\t{$src2, $dst|$dst, $src2}", "cmp${cc}ss\t{$src2, $dst|$dst, $src2}",
"cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S, "cmpss\t{$cc, $src2, $dst|$dst, $src2, $cc}", SSE_ALU_F32S>,
i8immZExt3>, XS; XS;
let ExeDomain = SSEPackedDouble in let ExeDomain = SSEPackedDouble in
defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64, defm CMPSD : sse12_cmp_scalar<FR64, f64mem, SSECC, X86cmps, f64, loadf64,
"cmp${cc}sd\t{$src2, $dst|$dst, $src2}", "cmp${cc}sd\t{$src2, $dst|$dst, $src2}",
"cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}", "cmpsd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
SSE_ALU_F64S, i8immZExt3>, XD; SSE_ALU_F64S>, XD;
} }
multiclass sse12_cmp_scalar_int<Operand memop, Operand CC, multiclass sse12_cmp_scalar_int<Operand memop, Operand CC,
Intrinsic Int, string asm, OpndItins itins, Intrinsic Int, string asm, OpndItins itins,
ImmLeaf immLeaf, ComplexPattern mem_cpat> { ComplexPattern mem_cpat> {
def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst), def rr : SIi8<0xC2, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src, CC:$cc), asm, (ins VR128:$src1, VR128:$src, CC:$cc), asm,
[(set VR128:$dst, (Int VR128:$src1, [(set VR128:$dst, (Int VR128:$src1,
VR128:$src, immLeaf:$cc))], VR128:$src, imm:$cc))],
itins.rr>, itins.rr>,
Sched<[itins.Sched]>; Sched<[itins.Sched]>;
let mayLoad = 1 in let mayLoad = 1 in
def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst), def rm : SIi8<0xC2, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, memop:$src, CC:$cc), asm, (ins VR128:$src1, memop:$src, CC:$cc), asm,
[(set VR128:$dst, (Int VR128:$src1, [(set VR128:$dst, (Int VR128:$src1,
mem_cpat:$src, immLeaf:$cc))], mem_cpat:$src, imm:$cc))],
itins.rm>, itins.rm>,
Sched<[itins.Sched.Folded, ReadAfterLd]>; Sched<[itins.Sched.Folded, ReadAfterLd]>;
} }
@ -2145,23 +2145,21 @@ let isCodeGenOnly = 1 in {
let ExeDomain = SSEPackedSingle in let ExeDomain = SSEPackedSingle in
defm Int_VCMPSS : sse12_cmp_scalar_int<ssmem, AVXCC, int_x86_sse_cmp_ss, defm Int_VCMPSS : sse12_cmp_scalar_int<ssmem, AVXCC, int_x86_sse_cmp_ss,
"cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}", "cmp${cc}ss\t{$src, $src1, $dst|$dst, $src1, $src}",
SSE_ALU_F32S, i8immZExt5, sse_load_f32>, SSE_ALU_F32S, sse_load_f32>, XS, VEX_4V;
XS, VEX_4V;
let ExeDomain = SSEPackedDouble in let ExeDomain = SSEPackedDouble in
defm Int_VCMPSD : sse12_cmp_scalar_int<sdmem, AVXCC, int_x86_sse2_cmp_sd, defm Int_VCMPSD : sse12_cmp_scalar_int<sdmem, AVXCC, int_x86_sse2_cmp_sd,
"cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}", "cmp${cc}sd\t{$src, $src1, $dst|$dst, $src1, $src}",
SSE_ALU_F32S, i8immZExt5, sse_load_f64>, // same latency as f32 SSE_ALU_F32S, sse_load_f64>, // same latency as f32
XD, VEX_4V; XD, VEX_4V;
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
let ExeDomain = SSEPackedSingle in let ExeDomain = SSEPackedSingle in
defm Int_CMPSS : sse12_cmp_scalar_int<ssmem, SSECC, int_x86_sse_cmp_ss, defm Int_CMPSS : sse12_cmp_scalar_int<ssmem, SSECC, int_x86_sse_cmp_ss,
"cmp${cc}ss\t{$src, $dst|$dst, $src}", "cmp${cc}ss\t{$src, $dst|$dst, $src}",
SSE_ALU_F32S, i8immZExt3, sse_load_f32>, XS; SSE_ALU_F32S, sse_load_f32>, XS;
let ExeDomain = SSEPackedDouble in let ExeDomain = SSEPackedDouble in
defm Int_CMPSD : sse12_cmp_scalar_int<sdmem, SSECC, int_x86_sse2_cmp_sd, defm Int_CMPSD : sse12_cmp_scalar_int<sdmem, SSECC, int_x86_sse2_cmp_sd,
"cmp${cc}sd\t{$src, $dst|$dst, $src}", "cmp${cc}sd\t{$src, $dst|$dst, $src}",
SSE_ALU_F64S, i8immZExt3, sse_load_f64>, SSE_ALU_F64S, sse_load_f64>, XD;
XD;
} }
} }
@ -2255,18 +2253,18 @@ let Defs = [EFLAGS] in {
// sse12_cmp_packed - sse 1 & 2 compare packed instructions // sse12_cmp_packed - sse 1 & 2 compare packed instructions
multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop, multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
Operand CC, ValueType VT, string asm, Operand CC, ValueType VT, string asm,
string asm_alt, Domain d, ImmLeaf immLeaf, string asm_alt, Domain d,
PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> { PatFrag ld_frag, OpndItins itins = SSE_ALU_F32P> {
let isCommutable = 1 in let isCommutable = 1 in
def rri : PIi8<0xC2, MRMSrcReg, def rri : PIi8<0xC2, MRMSrcReg,
(outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm, (outs RC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
[(set RC:$dst, (VT (X86cmpp RC:$src1, RC:$src2, immLeaf:$cc)))], [(set RC:$dst, (VT (X86cmpp RC:$src1, RC:$src2, imm:$cc)))],
itins.rr, d>, itins.rr, d>,
Sched<[WriteFAdd]>; Sched<[WriteFAdd]>;
def rmi : PIi8<0xC2, MRMSrcMem, def rmi : PIi8<0xC2, MRMSrcMem,
(outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
[(set RC:$dst, [(set RC:$dst,
(VT (X86cmpp RC:$src1, (ld_frag addr:$src2), immLeaf:$cc)))], (VT (X86cmpp RC:$src1, (ld_frag addr:$src2), imm:$cc)))],
itins.rm, d>, itins.rm, d>,
Sched<[WriteFAddLd, ReadAfterLd]>; Sched<[WriteFAddLd, ReadAfterLd]>;
@ -2286,28 +2284,28 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, v4f32, defm VCMPPS : sse12_cmp_packed<VR128, f128mem, AVXCC, v4f32,
"cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSEPackedSingle, i8immZExt5, loadv4f32>, PS, VEX_4V, VEX_WIG; SSEPackedSingle, loadv4f32>, PS, VEX_4V, VEX_WIG;
defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, v2f64, defm VCMPPD : sse12_cmp_packed<VR128, f128mem, AVXCC, v2f64,
"cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSEPackedDouble, i8immZExt5, loadv2f64>, PD, VEX_4V, VEX_WIG; SSEPackedDouble, loadv2f64>, PD, VEX_4V, VEX_WIG;
defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, v8f32, defm VCMPPSY : sse12_cmp_packed<VR256, f256mem, AVXCC, v8f32,
"cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSEPackedSingle, i8immZExt5, loadv8f32>, PS, VEX_4V, VEX_L; SSEPackedSingle, loadv8f32>, PS, VEX_4V, VEX_L;
defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, v4f64, defm VCMPPDY : sse12_cmp_packed<VR256, f256mem, AVXCC, v4f64,
"cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}", "cmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
"cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}", "cmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
SSEPackedDouble, i8immZExt5, loadv4f64>, PD, VEX_4V, VEX_L; SSEPackedDouble, loadv4f64>, PD, VEX_4V, VEX_L;
let Constraints = "$src1 = $dst" in { let Constraints = "$src1 = $dst" in {
defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, v4f32, defm CMPPS : sse12_cmp_packed<VR128, f128mem, SSECC, v4f32,
"cmp${cc}ps\t{$src2, $dst|$dst, $src2}", "cmp${cc}ps\t{$src2, $dst|$dst, $src2}",
"cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}", "cmpps\t{$cc, $src2, $dst|$dst, $src2, $cc}",
SSEPackedSingle, i8immZExt5, memopv4f32, SSE_ALU_F32P>, PS; SSEPackedSingle, memopv4f32, SSE_ALU_F32P>, PS;
defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, v2f64, defm CMPPD : sse12_cmp_packed<VR128, f128mem, SSECC, v2f64,
"cmp${cc}pd\t{$src2, $dst|$dst, $src2}", "cmp${cc}pd\t{$src2, $dst|$dst, $src2}",
"cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}", "cmppd\t{$cc, $src2, $dst|$dst, $src2, $cc}",
SSEPackedDouble, i8immZExt5, memopv2f64, SSE_ALU_F64P>, PD; SSEPackedDouble, memopv2f64, SSE_ALU_F64P>, PD;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

4
llvm/lib/Target/X86/X86InstrXOP.td
View File

@ -213,7 +213,7 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
"\t{$src2, $src1, $dst|$dst, $src1, $src2}"), "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
[(set VR128:$dst, [(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2), (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
i8immZExt3:$cc)))]>, imm:$cc)))]>,
XOP_4V; XOP_4V;
def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, i128mem:$src2, XOPCC:$cc), (ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
@ -222,7 +222,7 @@ multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128>
[(set VR128:$dst, [(set VR128:$dst,
(vt128 (OpNode (vt128 VR128:$src1), (vt128 (OpNode (vt128 VR128:$src1),
(vt128 (bitconvert (loadv2i64 addr:$src2))), (vt128 (bitconvert (loadv2i64 addr:$src2))),
i8immZExt3:$cc)))]>, imm:$cc)))]>,
XOP_4V; XOP_4V;
let isAsmParserOnly = 1, hasSideEffects = 0 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst), def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),