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[X86] Add patterns for using masked vptestnmd for 256-bit vectors without VLX. 

We can widen the mask and extract it back down.

llvm-svn: 323610
This commit is contained in:
Craig Topper 2018-01-27 23:49:14 +00:00
parent 540daee124
commit 5e4b45361f
2 changed files with 26 additions and 16 deletions
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37
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -2958,19 +2958,19 @@ defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86kshiftr, SSE_PSHU
multiclass axv512_icmp_packed_no_vlx_lowering<PatFrag Frag, string InstStr,
X86VectorVTInfo Narrow,
X86VectorVTInfo Wide> {
def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1),
def : Pat<(Narrow.KVT (Frag (Narrow.VT Narrow.RC:$src1),
(Narrow.VT Narrow.RC:$src2))),
(COPY_TO_REGCLASS
(!cast<Instruction>(InstStr##Zrr)
(!cast<Instruction>(InstStr#"Zrr")
(Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
(Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))),
Narrow.KRC)>;
def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
(Frag (Narrow.VT Narrow.RC:$src1),
def : Pat<(Narrow.KVT (and Narrow.KRC:$mask,
(Frag (Narrow.VT Narrow.RC:$src1),
(Narrow.VT Narrow.RC:$src2)))),
(COPY_TO_REGCLASS
(!cast<Instruction>(InstStr##Zrrk)
(!cast<Instruction>(InstStr#"Zrrk")
(COPY_TO_REGCLASS Narrow.KRC:$mask, Wide.KRC),
(Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src1, Narrow.SubRegIdx)),
(Wide.VT (INSERT_SUBREG (IMPLICIT_DEF), Narrow.RC:$src2, Narrow.SubRegIdx))),
@ -5232,14 +5232,25 @@ multiclass avx512_vptest_mb<bits<8> opc, string OpcodeStr, SDNode OpNode,
// Use 512bit version to implement 128/256 bit in case NoVLX.
multiclass avx512_vptest_lowering<SDNode OpNode, X86VectorVTInfo ExtendInfo,
X86VectorVTInfo _, string Suffix> {
def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))),
(_.KVT (COPY_TO_REGCLASS
(!cast<Instruction>(NAME # Suffix # "Zrr")
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src1, _.SubRegIdx),
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src2, _.SubRegIdx)),
_.KRC))>;
def : Pat<(_.KVT (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))),
(_.KVT (COPY_TO_REGCLASS
(!cast<Instruction>(NAME # Suffix # "Zrr")
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src1, _.SubRegIdx),
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src2, _.SubRegIdx)),
_.KRC))>;
def : Pat<(_.KVT (and _.KRC:$mask,
(OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))),
(COPY_TO_REGCLASS
(!cast<Instruction>(NAME # Suffix # "Zrrk")
(COPY_TO_REGCLASS _.KRC:$mask, ExtendInfo.KRC),
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src1, _.SubRegIdx),
(INSERT_SUBREG (ExtendInfo.VT (IMPLICIT_DEF)),
_.RC:$src2, _.SubRegIdx)),
_.KRC)>;
}
multiclass avx512_vptest_dq_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,

5
llvm/test/CodeGen/X86/avx512vl-vec-cmp.ll
View File

@ -1134,9 +1134,8 @@ define <8 x i32> @testnm_and(<8 x i32> %a, <8 x i32> %b, <8 x i32> %x, <8 x i32>
; NoVLX-NEXT: # kill: def %ymm2 killed %ymm2 def %zmm2
; NoVLX-NEXT: # kill: def %ymm1 killed %ymm1 def %zmm1
; NoVLX-NEXT: # kill: def %ymm0 killed %ymm0 def %zmm0
; NoVLX-NEXT: vptestnmd %zmm0, %zmm0, %k0
; NoVLX-NEXT: vptestnmd %zmm1, %zmm1, %k1
; NoVLX-NEXT: kandw %k1, %k0, %k1
; NoVLX-NEXT: vptestnmd %zmm0, %zmm0, %k1
; NoVLX-NEXT: vptestnmd %zmm1, %zmm1, %k1 {%k1}
; NoVLX-NEXT: vpblendmd %zmm2, %zmm3, %zmm0 {%k1}
; NoVLX-NEXT: # kill: def %ymm0 killed %ymm0 killed %zmm0
; NoVLX-NEXT: retq