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[AArch64][GlobalISel] Perform load/store extended reg folding with optsize 

GlobalISel was only doing this with minsize. SDAG does this with optsize.

(See: `SelectionDAG::shouldOptForSize()`)

This is a 0.3% code size improvement for CTMark at -Os.

(Best: 1.1% improvements on lencod + pairlocalalign)

Differential Revision: https://reviews.llvm.org/D96451
This commit is contained in:
Jessica Paquette 2021-02-10 14:07:36 -08:00
parent 3a5f8a3ea3
commit 5f7a4d8d05
2 changed files with 2 additions and 2 deletions
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2
llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
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@ -5219,7 +5219,7 @@ bool AArch64InstructionSelector::isWorthFoldingIntoExtendedReg(
// Always fold if there is one use, or if we're optimizing for size. // Always fold if there is one use, or if we're optimizing for size.
Register DefReg = MI.getOperand(0).getReg(); Register DefReg = MI.getOperand(0).getReg();
if (MRI.hasOneNonDBGUse(DefReg) || if (MRI.hasOneNonDBGUse(DefReg) ||
MI.getParent()->getParent()->getFunction().hasMinSize()) MI.getParent()->getParent()->getFunction().hasOptSize())
return true; return true;
// It's better to avoid folding and recomputing shifts when we don't have a // It's better to avoid folding and recomputing shifts when we don't have a

2
llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
View File

@ -23,7 +23,7 @@
define void @ldrhrox(i64* %addr) { ret void } define void @ldrhrox(i64* %addr) { ret void }
define void @ldbbrox(i64* %addr) { ret void } define void @ldbbrox(i64* %addr) { ret void }
define void @ldrqrox(i64* %addr) { ret void } define void @ldrqrox(i64* %addr) { ret void }
attributes #0 = { optsize minsize } attributes #0 = { optsize }
attributes #1 = { "target-features"="+lsl-fast" } attributes #1 = { "target-features"="+lsl-fast" }
... ...