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[RISCV] Replace a custom SDTypeProfile with SDTIntBinOp which should be sufficient here. 

On the surface this would be slightly less optimal for the isel
table, but due to a tablegen issue with HW mode this ends up
generating a smaller isel table.
This commit is contained in:
Craig Topper 2020-12-05 20:10:25 -08:00
parent b00f345acd
commit 5fc8f90f0a
1 changed files with 4 additions and 7 deletions
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11
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
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@ -716,13 +716,10 @@ let Predicates = [HasStdExtZbs] in
def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)), def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
(SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>; (SBEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
def SDT_RISCVGREVGORC : SDTypeProfile<1, 2, [SDTCisVT<0, XLenVT>, def riscv_grevi : SDNode<"RISCVISD::GREVI", SDTIntBinOp, []>;
SDTCisSameAs<0, 1>, def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDTIntBinOp, []>;
SDTCisSameAs<1, 2>]>; def riscv_gorci : SDNode<"RISCVISD::GORCI", SDTIntBinOp, []>;
def riscv_grevi : SDNode<"RISCVISD::GREVI", SDT_RISCVGREVGORC, []>; def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDTIntBinOp, []>;
def riscv_greviw : SDNode<"RISCVISD::GREVIW", SDT_RISCVGREVGORC, []>;
def riscv_gorci : SDNode<"RISCVISD::GORCI", SDT_RISCVGREVGORC, []>;
def riscv_gorciw : SDNode<"RISCVISD::GORCIW", SDT_RISCVGREVGORC, []>;
let Predicates = [HasStdExtZbp] in { let Predicates = [HasStdExtZbp] in {
def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>; def : Pat<(riscv_grevi GPR:$rs1, timm:$shamt), (GREVI GPR:$rs1, timm:$shamt)>;