[x86] add tests for phaddd/phaddw; NFC
More tests related to PR39195: https://bugs.llvm.org/show_bug.cgi?id=39195 If we limit the horizontal codegen, it may require different constraints for FP and integer. llvm-svn: 343994
This commit is contained in:
Sanjay Patel
parent
67b1b328f7
commit
6205ba0e7f
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@ -283,3 +283,243 @@ define <4 x i32> @phsubd1_reverse(<4 x i32> %x, <4 x i32> %y) {
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ret <4 x i32> %r
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ret <4 x i32> %r
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}
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}
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define <4 x i32> @phaddd_single_source1(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source1:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,2]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSSE3-NEXT: paddd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,2]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 2>
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%r = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 3>
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%add = add <4 x i32> %l, %r
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ret <4 x i32> %add
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}
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define <4 x i32> @phaddd_single_source2(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source2:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,2]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSSE3-NEXT: paddd %xmm1, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,2,3]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source2:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,2]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,2,3]
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 2>
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%r = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 3>
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%add = add <4 x i32> %l, %r
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%shuffle2 = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 undef, i32 undef>
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ret <4 x i32> %shuffle2
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}
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define <4 x i32> @phaddd_single_source3(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source3:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSSE3-NEXT: paddd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source3:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>
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%r = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 undef>
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%add = add <4 x i32> %l, %r
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ret <4 x i32> %add
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}
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define <4 x i32> @phaddd_single_source4(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source4:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,2,2]
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; SSSE3-NEXT: paddd %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source4:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,2,2]
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
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%add = add <4 x i32> %l, %x
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ret <4 x i32> %add
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}
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define <4 x i32> @phaddd_single_source5(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source5:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,2,2]
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; SSSE3-NEXT: paddd %xmm0, %xmm1
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm1[3,1,2,3]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source5:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,2,2]
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 undef, i32 2>
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%add = add <4 x i32> %l, %x
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%shuffle2 = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef>
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ret <4 x i32> %shuffle2
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}
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define <4 x i32> @phaddd_single_source6(<4 x i32> %x) {
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; SSSE3-LABEL: phaddd_single_source6:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,1,3]
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; SSSE3-NEXT: paddd %xmm1, %xmm0
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddd_single_source6:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; AVX-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; AVX-NEXT: vpaddd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,2,3,3]
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; AVX-NEXT: retq
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%l = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 undef>
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%r = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 1, i32 undef>
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%add = add <4 x i32> %l, %r
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%shuffle2 = shufflevector <4 x i32> %add, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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ret <4 x i32> %shuffle2
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}
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define <8 x i16> @phaddw_single_source1(<8 x i16> %x) {
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; SSSE3-LABEL: phaddw_single_source1:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movdqa %xmm0, %xmm1
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; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,4,5,6,7,0,1,4,5,8,9,12,13]
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; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[6,7,2,3,4,5,6,7,2,3,6,7,10,11,14,15]
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; SSSE3-NEXT: paddw %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddw_single_source1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufb {{.*#+}} xmm1 = xmm0[0,1,4,5,4,5,6,7,0,1,4,5,8,9,12,13]
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; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[6,7,2,3,4,5,6,7,2,3,6,7,10,11,14,15]
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; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 2, i32 4, i32 6>
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%r = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>
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%add = add <8 x i16> %l, %r
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ret <8 x i16> %add
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}
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define <8 x i16> @phaddw_single_source2(<8 x i16> %x) {
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; SSSE3-LABEL: phaddw_single_source2:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
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; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; SSSE3-NEXT: paddw %xmm1, %xmm0
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; SSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,6,7]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddw_single_source2:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
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; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,4,6,7]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,1,2,3]
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; AVX-NEXT: retq
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%l = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 2, i32 4, i32 6>
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%r = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 5, i32 7>
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%add = add <8 x i16> %l, %r
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%shuffle2 = shufflevector <8 x i16> %add, <8 x i16> undef, <8 x i32> <i32 5, i32 4, i32 3, i32 2, i32 undef, i32 undef, i32 undef, i32 undef>
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ret <8 x i16> %shuffle2
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}
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define <8 x i16> @phaddw_single_source3(<8 x i16> %x) {
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; SSSE3-LABEL: phaddw_single_source3:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
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; SSSE3-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; SSSE3-NEXT: paddw %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddw_single_source3:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshuflw {{.*#+}} xmm1 = xmm0[0,2,2,3,4,5,6,7]
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,3]
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; AVX-NEXT: vpshuflw {{.*#+}} xmm0 = xmm0[1,3,2,3,4,5,6,7]
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; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 2, i32 undef, i32 undef>
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%r = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 3, i32 undef, i32 undef>
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%add = add <8 x i16> %l, %r
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ret <8 x i16> %add
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}
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define <8 x i16> @phaddw_single_source4(<8 x i16> %x) {
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; SSSE3-LABEL: phaddw_single_source4:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movdqa %xmm0, %xmm1
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; SSSE3-NEXT: pslld $16, %xmm1
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; SSSE3-NEXT: paddw %xmm0, %xmm1
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddw_single_source4:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $16, %xmm0, %xmm1
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; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX-NEXT: retq
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%l = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 6>
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%add = add <8 x i16> %l, %x
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ret <8 x i16> %add
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}
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define <8 x i16> @phaddw_single_source6(<8 x i16> %x) {
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; SSSE3-LABEL: phaddw_single_source6:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,3]
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; SSSE3-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,5,6,7]
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; SSSE3-NEXT: paddw %xmm1, %xmm0
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; SSSE3-NEXT: psrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
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; SSSE3-NEXT: retq
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;
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; AVX-LABEL: phaddw_single_source6:
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; AVX: # %bb.0:
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; AVX-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[0,1,0,1]
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; AVX-NEXT: vpmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero
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; AVX-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vpsrldq {{.*#+}} xmm0 = xmm0[6,7,8,9,10,11,12,13,14,15],zero,zero,zero,zero,zero,zero
|
||||||
|
; AVX-NEXT: retq
|
||||||
|
%l = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef>
|
||||||
|
%r = shufflevector <8 x i16> %x, <8 x i16> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 undef, i32 undef, i32 undef>
|
||||||
|
%add = add <8 x i16> %l, %r
|
||||||
|
%shuffle2 = shufflevector <8 x i16> %add, <8 x i16> undef, <8 x i32> <i32 undef, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
||||||
|
ret <8 x i16> %shuffle2
|
||||||
|
}
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue