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[Hexagon] Add assertions about V6_pred_scalar2

This commit is contained in:
Krzysztof Parzyszek 2020-09-05 18:15:38 -05:00
parent 9518f032e4
commit 62f89a89f3
1 changed files with 5 additions and 0 deletions
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5
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -631,6 +631,9 @@ HexagonTargetLowering::createHvxPrefixPred(SDValue PredV, const SDLoc &dl,
if (!ZeroFill)
return S;
// Fill the bytes beyond BlockLen with 0s.
// V6_pred_scalar2 cannot fill the entire predicate, so it only works
// when BlockLen < HwLen.
assert(BlockLen < HwLen && "vsetq(v1) prerequisite");
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
{DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
@ -1094,6 +1097,7 @@ HexagonTargetLowering::insertHvxSubvectorPred(SDValue VecV, SDValue SubV,
// ByteVec is the target vector VecV rotated in such a way that the
// subvector should be inserted at index 0. Generate a predicate mask
// and use vmux to do the insertion.
assert(BlockLen < HwLen && "vsetq(v1) prerequisite");
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
SDValue Q = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
{DAG.getConstant(BlockLen, dl, MVT::i32)}, DAG);
@ -1906,6 +1910,7 @@ HexagonTargetLowering::WidenHvxStore(SDValue Op, SelectionDAG &DAG) const {
}
assert(ty(Value).getVectorNumElements() == HwLen); // Paranoia
assert(ValueLen < HwLen && "vsetq(v1) prerequisite");
MVT BoolTy = MVT::getVectorVT(MVT::i1, HwLen);
SDValue StoreQ = getInstr(Hexagon::V6_pred_scalar2, dl, BoolTy,
{DAG.getConstant(ValueLen, dl, MVT::i32)}, DAG);