[MIPS64] Emulate MSA branch instructions
This patch adds MSA branch instruction emulation for MIPS64. Reviewers: tberghammer, jaydeep Subscribers: tberghammer, lldb-commits, nitesh.jain, mohit.bhakkad (Mohit Bhakkad), bhushan (Bhushan Attarde) Differential: http://reviews.llvm.org/D12356 llvm-svn: 246745
This commit is contained in:
Sagar Thakur
parent
0d5a2bd6f7
commit
66089382d9
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@ -221,41 +221,76 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name
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{
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switch (reg_num)
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{
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case gcc_dwarf_sp_mips64: return "r29";
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case gcc_dwarf_r30_mips64: return "r30";
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case gcc_dwarf_ra_mips64: return "r31";
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case gcc_dwarf_f0_mips64: return "f0";
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case gcc_dwarf_f1_mips64: return "f1";
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case gcc_dwarf_f2_mips64: return "f2";
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case gcc_dwarf_f3_mips64: return "f3";
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case gcc_dwarf_f4_mips64: return "f4";
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case gcc_dwarf_f5_mips64: return "f5";
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case gcc_dwarf_f6_mips64: return "f6";
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case gcc_dwarf_f7_mips64: return "f7";
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case gcc_dwarf_f8_mips64: return "f8";
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case gcc_dwarf_f9_mips64: return "f9";
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case gcc_dwarf_f10_mips64: return "f10";
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case gcc_dwarf_f11_mips64: return "f11";
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case gcc_dwarf_f12_mips64: return "f12";
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case gcc_dwarf_f13_mips64: return "f13";
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case gcc_dwarf_f14_mips64: return "f14";
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case gcc_dwarf_f15_mips64: return "f15";
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case gcc_dwarf_f16_mips64: return "f16";
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case gcc_dwarf_f17_mips64: return "f17";
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case gcc_dwarf_f18_mips64: return "f18";
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case gcc_dwarf_f19_mips64: return "f19";
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case gcc_dwarf_f20_mips64: return "f20";
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case gcc_dwarf_f21_mips64: return "f21";
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case gcc_dwarf_f22_mips64: return "f22";
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case gcc_dwarf_f23_mips64: return "f23";
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case gcc_dwarf_f24_mips64: return "f24";
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case gcc_dwarf_f25_mips64: return "f25";
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case gcc_dwarf_f26_mips64: return "f26";
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case gcc_dwarf_f27_mips64: return "f27";
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case gcc_dwarf_f28_mips64: return "f28";
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case gcc_dwarf_f29_mips64: return "f29";
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case gcc_dwarf_f30_mips64: return "f30";
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case gcc_dwarf_f31_mips64: return "f31";
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case gcc_dwarf_sp_mips64: return "r29";
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case gcc_dwarf_r30_mips64: return "r30";
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case gcc_dwarf_ra_mips64: return "r31";
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case gcc_dwarf_f0_mips64: return "f0";
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case gcc_dwarf_f1_mips64: return "f1";
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case gcc_dwarf_f2_mips64: return "f2";
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case gcc_dwarf_f3_mips64: return "f3";
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case gcc_dwarf_f4_mips64: return "f4";
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case gcc_dwarf_f5_mips64: return "f5";
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case gcc_dwarf_f6_mips64: return "f6";
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case gcc_dwarf_f7_mips64: return "f7";
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case gcc_dwarf_f8_mips64: return "f8";
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case gcc_dwarf_f9_mips64: return "f9";
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case gcc_dwarf_f10_mips64: return "f10";
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case gcc_dwarf_f11_mips64: return "f11";
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case gcc_dwarf_f12_mips64: return "f12";
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case gcc_dwarf_f13_mips64: return "f13";
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case gcc_dwarf_f14_mips64: return "f14";
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case gcc_dwarf_f15_mips64: return "f15";
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case gcc_dwarf_f16_mips64: return "f16";
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case gcc_dwarf_f17_mips64: return "f17";
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case gcc_dwarf_f18_mips64: return "f18";
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case gcc_dwarf_f19_mips64: return "f19";
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case gcc_dwarf_f20_mips64: return "f20";
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case gcc_dwarf_f21_mips64: return "f21";
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case gcc_dwarf_f22_mips64: return "f22";
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case gcc_dwarf_f23_mips64: return "f23";
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case gcc_dwarf_f24_mips64: return "f24";
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case gcc_dwarf_f25_mips64: return "f25";
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case gcc_dwarf_f26_mips64: return "f26";
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case gcc_dwarf_f27_mips64: return "f27";
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case gcc_dwarf_f28_mips64: return "f28";
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case gcc_dwarf_f29_mips64: return "f29";
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case gcc_dwarf_f30_mips64: return "f30";
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case gcc_dwarf_f31_mips64: return "f31";
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case gcc_dwarf_w0_mips64: return "w0";
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case gcc_dwarf_w1_mips64: return "w1";
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case gcc_dwarf_w2_mips64: return "w2";
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case gcc_dwarf_w3_mips64: return "w3";
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case gcc_dwarf_w4_mips64: return "w4";
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case gcc_dwarf_w5_mips64: return "w5";
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case gcc_dwarf_w6_mips64: return "w6";
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case gcc_dwarf_w7_mips64: return "w7";
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case gcc_dwarf_w8_mips64: return "w8";
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case gcc_dwarf_w9_mips64: return "w9";
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case gcc_dwarf_w10_mips64: return "w10";
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case gcc_dwarf_w11_mips64: return "w11";
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case gcc_dwarf_w12_mips64: return "w12";
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case gcc_dwarf_w13_mips64: return "w13";
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case gcc_dwarf_w14_mips64: return "w14";
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case gcc_dwarf_w15_mips64: return "w15";
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case gcc_dwarf_w16_mips64: return "w16";
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case gcc_dwarf_w17_mips64: return "w17";
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case gcc_dwarf_w18_mips64: return "w18";
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case gcc_dwarf_w19_mips64: return "w19";
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case gcc_dwarf_w20_mips64: return "w20";
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case gcc_dwarf_w21_mips64: return "w21";
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case gcc_dwarf_w22_mips64: return "w22";
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case gcc_dwarf_w23_mips64: return "w23";
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case gcc_dwarf_w24_mips64: return "w24";
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case gcc_dwarf_w25_mips64: return "w25";
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case gcc_dwarf_w26_mips64: return "w26";
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case gcc_dwarf_w27_mips64: return "w27";
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case gcc_dwarf_w28_mips64: return "w28";
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case gcc_dwarf_w29_mips64: return "w29";
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case gcc_dwarf_w30_mips64: return "w30";
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case gcc_dwarf_w31_mips64: return "w31";
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case gcc_dwarf_mir_mips64: return "mir";
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case gcc_dwarf_mcsr_mips64: return "mcsr";
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case gcc_dwarf_config5_mips64: return "config5";
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default:
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break;
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}
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@ -336,6 +371,41 @@ EmulateInstructionMIPS64::GetRegisterName (unsigned reg_num, bool alternate_name
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case gcc_dwarf_f31_mips64: return "f31";
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case gcc_dwarf_fcsr_mips64: return "fcsr";
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case gcc_dwarf_fir_mips64: return "fir";
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case gcc_dwarf_w0_mips64: return "w0";
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case gcc_dwarf_w1_mips64: return "w1";
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case gcc_dwarf_w2_mips64: return "w2";
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case gcc_dwarf_w3_mips64: return "w3";
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case gcc_dwarf_w4_mips64: return "w4";
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case gcc_dwarf_w5_mips64: return "w5";
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case gcc_dwarf_w6_mips64: return "w6";
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case gcc_dwarf_w7_mips64: return "w7";
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case gcc_dwarf_w8_mips64: return "w8";
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case gcc_dwarf_w9_mips64: return "w9";
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case gcc_dwarf_w10_mips64: return "w10";
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case gcc_dwarf_w11_mips64: return "w11";
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case gcc_dwarf_w12_mips64: return "w12";
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case gcc_dwarf_w13_mips64: return "w13";
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case gcc_dwarf_w14_mips64: return "w14";
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case gcc_dwarf_w15_mips64: return "w15";
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case gcc_dwarf_w16_mips64: return "w16";
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case gcc_dwarf_w17_mips64: return "w17";
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case gcc_dwarf_w18_mips64: return "w18";
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case gcc_dwarf_w19_mips64: return "w19";
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case gcc_dwarf_w20_mips64: return "w20";
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case gcc_dwarf_w21_mips64: return "w21";
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case gcc_dwarf_w22_mips64: return "w22";
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case gcc_dwarf_w23_mips64: return "w23";
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case gcc_dwarf_w24_mips64: return "w24";
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case gcc_dwarf_w25_mips64: return "w25";
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case gcc_dwarf_w26_mips64: return "w26";
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case gcc_dwarf_w27_mips64: return "w27";
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case gcc_dwarf_w28_mips64: return "w28";
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case gcc_dwarf_w29_mips64: return "w29";
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case gcc_dwarf_w30_mips64: return "w30";
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case gcc_dwarf_w31_mips64: return "w31";
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case gcc_dwarf_mcsr_mips64: return "mcsr";
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case gcc_dwarf_mir_mips64: return "mir";
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case gcc_dwarf_config5_mips64: return "config5";
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}
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return nullptr;
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}
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@ -362,7 +432,7 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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::memset (®_info, 0, sizeof(RegisterInfo));
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::memset (reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
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if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64)
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if (reg_num == gcc_dwarf_sr_mips64 || reg_num == gcc_dwarf_fcsr_mips64 || reg_num == gcc_dwarf_fir_mips64 || reg_num == gcc_dwarf_mcsr_mips64 || reg_num == gcc_dwarf_mir_mips64 || reg_num == gcc_dwarf_config5_mips64)
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{
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reg_info.byte_size = 4;
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reg_info.format = eFormatHex;
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@ -374,6 +444,12 @@ EmulateInstructionMIPS64::GetRegisterInfo (RegisterKind reg_kind, uint32_t reg_n
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reg_info.format = eFormatHex;
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reg_info.encoding = eEncodingUint;
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}
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else if ((int)reg_num >= gcc_dwarf_w0_mips64 && (int)reg_num <= gcc_dwarf_w31_mips64)
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{
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reg_info.byte_size = 16;
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reg_info.format = eFormatVectorOfUInt8;
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reg_info.encoding = eEncodingVector;
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}
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else
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{
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return false;
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@ -474,6 +550,16 @@ EmulateInstructionMIPS64::GetOpcodeForInstruction (const char *op_name)
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{ "BC1ANY2T", &EmulateInstructionMIPS64::Emulate_BC1ANY2T, "BC1ANY2T cc, offset" },
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{ "BC1ANY4F", &EmulateInstructionMIPS64::Emulate_BC1ANY4F, "BC1ANY4F cc, offset" },
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{ "BC1ANY4T", &EmulateInstructionMIPS64::Emulate_BC1ANY4T, "BC1ANY4T cc, offset" },
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{ "BNZ_B", &EmulateInstructionMIPS64::Emulate_BNZB, "BNZ.b wt,s16" },
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{ "BNZ_H", &EmulateInstructionMIPS64::Emulate_BNZH, "BNZ.h wt,s16" },
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{ "BNZ_W", &EmulateInstructionMIPS64::Emulate_BNZW, "BNZ.w wt,s16" },
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{ "BNZ_D", &EmulateInstructionMIPS64::Emulate_BNZD, "BNZ.d wt,s16" },
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{ "BZ_B", &EmulateInstructionMIPS64::Emulate_BZB, "BZ.b wt,s16" },
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{ "BZ_H", &EmulateInstructionMIPS64::Emulate_BZH, "BZ.h wt,s16" },
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{ "BZ_W", &EmulateInstructionMIPS64::Emulate_BZW, "BZ.w wt,s16" },
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{ "BZ_D", &EmulateInstructionMIPS64::Emulate_BZD, "BZ.d wt,s16" },
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{ "BNZ_V", &EmulateInstructionMIPS64::Emulate_BNZV, "BNZ.V wt,s16" },
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{ "BZ_V", &EmulateInstructionMIPS64::Emulate_BZV, "BZ.V wt,s16" },
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};
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static const size_t k_num_mips_opcodes = llvm::array_lengthof(g_opcodes);
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@ -2996,3 +3082,159 @@ EmulateInstructionMIPS64::Emulate_BC1ANY4T (llvm::MCInst& insn)
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BNZB (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 1, true);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BNZH (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 2, true);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BNZW (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 4, true);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BNZD (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 8, true);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BZB (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 1, false);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BZH (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 2, false);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BZW (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 4, false);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BZD (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_DF(insn, 8, false);
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}
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bool
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EmulateInstructionMIPS64::Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz)
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{
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bool success = false, branch_hit = true;
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int64_t target = 0;
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RegisterValue reg_value;
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uint8_t * ptr = NULL;
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uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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int64_t offset = insn.getOperand(1).getImm();
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int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips64 + wt, reg_value))
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ptr = (uint8_t *)reg_value.GetBytes();
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else
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return false;
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for(int i = 0; i < 16 / element_byte_size; i++)
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{
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switch(element_byte_size)
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{
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case 1:
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if((*ptr == 0 && bnz) || (*ptr != 0 && !bnz) )
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branch_hit = false;
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break;
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case 2:
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if((*(uint16_t *)ptr == 0 && bnz) || (*(uint16_t *)ptr != 0 && !bnz))
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branch_hit = false;
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break;
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case 4:
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if((*(uint32_t *)ptr == 0 && bnz) || (*(uint32_t *)ptr != 0 && !bnz))
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branch_hit = false;
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break;
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case 8:
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if((*(uint64_t *)ptr == 0 && bnz) || (*(uint64_t *)ptr != 0 && !bnz))
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branch_hit = false;
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break;
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}
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if(!branch_hit)
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break;
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ptr = ptr + element_byte_size;
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}
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if(branch_hit)
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target = pc + offset;
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else
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target = pc + 8;
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Context context;
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context.type = eContextRelativeBranchImmediate;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
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return true;
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}
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bool
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EmulateInstructionMIPS64::Emulate_BNZV (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_V (insn, true);
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}
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bool
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EmulateInstructionMIPS64::Emulate_BZV (llvm::MCInst& insn)
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{
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return Emulate_MSA_Branch_V (insn, false);
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}
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bool
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EmulateInstructionMIPS64::Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz)
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{
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bool success = false;
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int64_t target = 0;
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llvm::APInt wr_val = llvm::APInt::getNullValue(128);
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llvm::APInt fail_value = llvm::APInt::getMaxValue(128);
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llvm::APInt zero_value = llvm::APInt::getNullValue(128);
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RegisterValue reg_value;
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uint32_t wt = m_reg_info->getEncodingValue (insn.getOperand(0).getReg());
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int64_t offset = insn.getOperand(1).getImm();
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int64_t pc = ReadRegisterUnsigned (eRegisterKindDWARF, gcc_dwarf_pc_mips64, 0, &success);
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if (!success)
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return false;
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if (ReadRegister (eRegisterKindDWARF, gcc_dwarf_w0_mips64 + wt, reg_value))
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wr_val = reg_value.GetAsUInt128(fail_value);
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else
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return false;
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if((llvm::APInt::isSameValue(zero_value, wr_val) && !bnz) || (!llvm::APInt::isSameValue(zero_value, wr_val) && bnz))
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target = pc + offset;
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else
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target = pc + 8;
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Context context;
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context.type = eContextRelativeBranchImmediate;
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if (!WriteRegisterUnsigned (context, eRegisterKindDWARF, gcc_dwarf_pc_mips64, target))
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return false;
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return true;
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}
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|||
|
|
@ -301,6 +301,42 @@ protected:
|
|||
bool
|
||||
Emulate_BC1ANY4T (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BNZB (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BNZH (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BNZW (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BNZD (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BZB (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BZH (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BZW (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BZD (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_MSA_Branch_DF (llvm::MCInst& insn, int element_byte_size, bool bnz);
|
||||
|
||||
bool
|
||||
Emulate_BNZV (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_BZV (llvm::MCInst& insn);
|
||||
|
||||
bool
|
||||
Emulate_MSA_Branch_V (llvm::MCInst& insn, bool bnz);
|
||||
|
||||
bool
|
||||
nonvolatile_reg_p (uint64_t regnum);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue