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These instructions have special lowering that may lower them to SSE 

instructions. Prevent that if we don't want implicit uses of SSE.

llvm-svn: 66877
This commit is contained in:
Bill Wendling 2009-03-13 08:41:47 +00:00
parent afc74e2326
commit 798fd56d0f
1 changed files with 19 additions and 12 deletions
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31
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -113,31 +113,38 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
if (Subtarget->is64Bit()) { if (Subtarget->is64Bit()) {
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand);
} else { } else {
if (X86ScalarSSEf64) { if (!UseSoftFloat && !NoImplicitFloat && X86ScalarSSEf64) {
// We have an impenetrably clever algorithm for ui64->double only. // We have an impenetrably clever algorithm for ui64->double only.
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);
// We have faster algorithm for ui32->single only. // We have faster algorithm for ui32->single only.
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
} else } else {
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
}
} }
// Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
// this operation. // this operation.
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
// SSE has no i16 to fp conversion, only i32
if (X86ScalarSSEf32) { if (!UseSoftFloat && !NoImplicitFloat) {
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); // SSE has no i16 to fp conversion, only i32
// f32 and f64 cases are Legal, f80 case is not if (X86ScalarSSEf32) {
setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
// f32 and f64 cases are Legal, f80 case is not
setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
} else {
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom);
setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom);
}
} else { } else {
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote);
} }
// In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64
@ -4975,8 +4982,8 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size); int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size);
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
StackSlot, StackSlot,
PseudoSourceValue::getFixedStack(SSFI), 0); PseudoSourceValue::getFixedStack(SSFI), 0);
// Build the FILD // Build the FILD
SDVTList Tys; SDVTList Tys;