[X86] Fix chains update when lowering BUILD_VECTOR to a vector load
The code which lowers BUILD_VECTOR of consecutive loads into a single vector load doesn't update chains properly. As a result the vector load can be reordered with the store to the same location. The current code in EltsFromConsecutiveLoads only updates the chain following the first load. The fix is to update the chains following all the loads comprising the vector. This is a fix for PR10114. Reviewed By: niravd Differential Revision: https://reviews.llvm.org/D38547 llvm-svn: 314988
This commit is contained in:
Artur Pilipenko
parent
aa0835a7ab
commit
7b15254c8f
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@ -6540,14 +6540,20 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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}
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}
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auto CreateLoad = [&DAG, &DL](EVT VT, LoadSDNode *LDBase) {
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SmallVector<LoadSDNode *, 8> Loads;
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for (int i = FirstLoadedElt; i <= LastLoadedElt; ++i)
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if (LoadMask[i])
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Loads.push_back(cast<LoadSDNode>(peekThroughBitcasts(Elts[i])));
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auto CreateLoad = [&DAG, &DL, &Loads](EVT VT, LoadSDNode *LDBase) {
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auto MMOFlags = LDBase->getMemOperand()->getFlags();
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assert(!(MMOFlags & MachineMemOperand::MOVolatile) &&
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"Cannot merge volatile loads.");
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SDValue NewLd =
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DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(),
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LDBase->getPointerInfo(), LDBase->getAlignment(), MMOFlags);
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DAG.makeEquivalentMemoryOrdering(LDBase, NewLd);
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for (auto *LD : Loads)
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DAG.makeEquivalentMemoryOrdering(LD, NewLd);
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return NewLd;
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};
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@ -6612,7 +6618,8 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, ArrayRef<SDValue> Elts,
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LDBase->getAlignment(),
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false/*isVolatile*/, true/*ReadMem*/,
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false/*WriteMem*/);
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DAG.makeEquivalentMemoryOrdering(LDBase, ResNode);
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for (auto *LD : Loads)
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DAG.makeEquivalentMemoryOrdering(LD, ResNode);
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return DAG.getBitcast(VT, ResNode);
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}
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}
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@ -409,6 +409,124 @@ define <4 x i32> @merge_4i32_i32_23u5(i32* %ptr) nounwind uwtable noinline ssp {
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ret <4 x i32> %res3
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}
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define <4 x i32> @merge_4i32_i32_23u5_inc2(i32* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_4i32_i32_23u5_inc2:
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; SSE: # BB#0:
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; SSE-NEXT: movups 8(%rdi), %xmm0
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; SSE-NEXT: incl 8(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: merge_4i32_i32_23u5_inc2:
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; AVX: # BB#0:
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; AVX-NEXT: vmovups 8(%rdi), %xmm0
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; AVX-NEXT: incl 8(%rdi)
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; AVX-NEXT: retq
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;
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; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc2:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi6:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi7:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: .Lcfi8:
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; X32-SSE1-NEXT: .cfi_offset %esi, -12
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; X32-SSE1-NEXT: .Lcfi9:
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; X32-SSE1-NEXT: .cfi_offset %edi, -8
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE1-NEXT: movl 8(%ecx), %edx
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; X32-SSE1-NEXT: movl 12(%ecx), %esi
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; X32-SSE1-NEXT: leal 1(%edx), %edi
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; X32-SSE1-NEXT: movl %edi, 8(%ecx)
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; X32-SSE1-NEXT: movl 20(%ecx), %ecx
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; X32-SSE1-NEXT: movl %esi, 4(%eax)
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; X32-SSE1-NEXT: movl %edx, (%eax)
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; X32-SSE1-NEXT: movl %ecx, 12(%eax)
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; X32-SSE1-NEXT: popl %esi
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; X32-SSE1-NEXT: popl %edi
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; X32-SSE1-NEXT: retl $4
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;
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; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc2:
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; X32-SSE41: # BB#0:
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: movups 8(%eax), %xmm0
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; X32-SSE41-NEXT: incl 8(%eax)
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; X32-SSE41-NEXT: retl
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%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 2
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%ptr1 = getelementptr inbounds i32, i32* %ptr, i64 3
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%ptr3 = getelementptr inbounds i32, i32* %ptr, i64 5
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%val0 = load i32, i32* %ptr0
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%inc = add i32 %val0, 1
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store i32 %inc, i32* %ptr0
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%val1 = load i32, i32* %ptr1
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%val3 = load i32, i32* %ptr3
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%res0 = insertelement <4 x i32> undef, i32 %val0, i32 0
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%res1 = insertelement <4 x i32> %res0, i32 %val1, i32 1
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%res3 = insertelement <4 x i32> %res1, i32 %val3, i32 3
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ret <4 x i32> %res3
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}
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define <4 x i32> @merge_4i32_i32_23u5_inc3(i32* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_4i32_i32_23u5_inc3:
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; SSE: # BB#0:
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; SSE-NEXT: movups 8(%rdi), %xmm0
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; SSE-NEXT: incl 12(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: merge_4i32_i32_23u5_inc3:
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; AVX: # BB#0:
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; AVX-NEXT: vmovups 8(%rdi), %xmm0
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; AVX-NEXT: incl 12(%rdi)
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; AVX-NEXT: retq
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;
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; X32-SSE1-LABEL: merge_4i32_i32_23u5_inc3:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi10:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi11:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: .Lcfi12:
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; X32-SSE1-NEXT: .cfi_offset %esi, -12
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; X32-SSE1-NEXT: .Lcfi13:
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; X32-SSE1-NEXT: .cfi_offset %edi, -8
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE1-NEXT: movl 8(%ecx), %edx
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; X32-SSE1-NEXT: movl 12(%ecx), %esi
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; X32-SSE1-NEXT: leal 1(%esi), %edi
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; X32-SSE1-NEXT: movl %edi, 12(%ecx)
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; X32-SSE1-NEXT: movl 20(%ecx), %ecx
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; X32-SSE1-NEXT: movl %esi, 4(%eax)
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; X32-SSE1-NEXT: movl %edx, (%eax)
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; X32-SSE1-NEXT: movl %ecx, 12(%eax)
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; X32-SSE1-NEXT: popl %esi
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; X32-SSE1-NEXT: popl %edi
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; X32-SSE1-NEXT: retl $4
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;
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; X32-SSE41-LABEL: merge_4i32_i32_23u5_inc3:
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; X32-SSE41: # BB#0:
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: movups 8(%eax), %xmm0
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; X32-SSE41-NEXT: incl 12(%eax)
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; X32-SSE41-NEXT: retl
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%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 2
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%ptr1 = getelementptr inbounds i32, i32* %ptr, i64 3
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%ptr3 = getelementptr inbounds i32, i32* %ptr, i64 5
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%val0 = load i32, i32* %ptr0
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%val1 = load i32, i32* %ptr1
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%inc = add i32 %val1, 1
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store i32 %inc, i32* %ptr1
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%val3 = load i32, i32* %ptr3
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%res0 = insertelement <4 x i32> undef, i32 %val0, i32 0
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%res1 = insertelement <4 x i32> %res0, i32 %val1, i32 1
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%res3 = insertelement <4 x i32> %res1, i32 %val3, i32 3
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ret <4 x i32> %res3
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}
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define <4 x i32> @merge_4i32_i32_3zuu(i32* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_4i32_i32_3zuu:
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; SSE: # BB#0:
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@ -513,6 +631,118 @@ define <4 x i32> @merge_4i32_i32_45zz(i32* %ptr) nounwind uwtable noinline ssp {
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ret <4 x i32> %res1
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}
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define <4 x i32> @merge_4i32_i32_45zz_inc4(i32* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_4i32_i32_45zz_inc4:
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; SSE: # BB#0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: incl 16(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: merge_4i32_i32_45zz_inc4:
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; AVX: # BB#0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: incl 16(%rdi)
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; AVX-NEXT: retq
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;
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; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc4:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi14:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi15:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: .Lcfi16:
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; X32-SSE1-NEXT: .cfi_offset %esi, -12
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; X32-SSE1-NEXT: .Lcfi17:
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; X32-SSE1-NEXT: .cfi_offset %edi, -8
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE1-NEXT: movl 16(%ecx), %edx
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; X32-SSE1-NEXT: movl 20(%ecx), %esi
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; X32-SSE1-NEXT: leal 1(%edx), %edi
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; X32-SSE1-NEXT: movl %edi, 16(%ecx)
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; X32-SSE1-NEXT: movl %esi, 4(%eax)
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; X32-SSE1-NEXT: movl %edx, (%eax)
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; X32-SSE1-NEXT: movl $0, 12(%eax)
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; X32-SSE1-NEXT: movl $0, 8(%eax)
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; X32-SSE1-NEXT: popl %esi
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; X32-SSE1-NEXT: popl %edi
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; X32-SSE1-NEXT: retl $4
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;
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; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc4:
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; X32-SSE41: # BB#0:
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X32-SSE41-NEXT: incl 16(%eax)
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; X32-SSE41-NEXT: retl
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%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 4
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%ptr1 = getelementptr inbounds i32, i32* %ptr, i64 5
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%val0 = load i32, i32* %ptr0
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%inc = add i32 %val0, 1
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store i32 %inc, i32* %ptr0
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%val1 = load i32, i32* %ptr1
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%res0 = insertelement <4 x i32> zeroinitializer, i32 %val0, i32 0
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%res1 = insertelement <4 x i32> %res0, i32 %val1, i32 1
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ret <4 x i32> %res1
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}
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define <4 x i32> @merge_4i32_i32_45zz_inc5(i32* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_4i32_i32_45zz_inc5:
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; SSE: # BB#0:
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: incl 20(%rdi)
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; SSE-NEXT: retq
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;
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; AVX-LABEL: merge_4i32_i32_45zz_inc5:
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; AVX: # BB#0:
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; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
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; AVX-NEXT: incl 20(%rdi)
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; AVX-NEXT: retq
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;
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; X32-SSE1-LABEL: merge_4i32_i32_45zz_inc5:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi18:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi19:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: .Lcfi20:
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; X32-SSE1-NEXT: .cfi_offset %esi, -12
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; X32-SSE1-NEXT: .Lcfi21:
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; X32-SSE1-NEXT: .cfi_offset %edi, -8
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-SSE1-NEXT: movl 16(%ecx), %edx
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; X32-SSE1-NEXT: movl 20(%ecx), %esi
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; X32-SSE1-NEXT: leal 1(%esi), %edi
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; X32-SSE1-NEXT: movl %edi, 20(%ecx)
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; X32-SSE1-NEXT: movl %esi, 4(%eax)
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; X32-SSE1-NEXT: movl %edx, (%eax)
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; X32-SSE1-NEXT: movl $0, 12(%eax)
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; X32-SSE1-NEXT: movl $0, 8(%eax)
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; X32-SSE1-NEXT: popl %esi
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; X32-SSE1-NEXT: popl %edi
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; X32-SSE1-NEXT: retl $4
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;
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; X32-SSE41-LABEL: merge_4i32_i32_45zz_inc5:
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; X32-SSE41: # BB#0:
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; X32-SSE41-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE41-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X32-SSE41-NEXT: incl 20(%eax)
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; X32-SSE41-NEXT: retl
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%ptr0 = getelementptr inbounds i32, i32* %ptr, i64 4
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%ptr1 = getelementptr inbounds i32, i32* %ptr, i64 5
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%val0 = load i32, i32* %ptr0
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%val1 = load i32, i32* %ptr1
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%inc = add i32 %val1, 1
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store i32 %inc, i32* %ptr1
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%res0 = insertelement <4 x i32> zeroinitializer, i32 %val0, i32 0
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%res1 = insertelement <4 x i32> %res0, i32 %val1, i32 1
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ret <4 x i32> %res1
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}
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define <8 x i16> @merge_8i16_i16_23u567u9(i16* %ptr) nounwind uwtable noinline ssp {
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; SSE-LABEL: merge_8i16_i16_23u567u9:
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; SSE: # BB#0:
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@ -527,14 +757,14 @@ define <8 x i16> @merge_8i16_i16_23u567u9(i16* %ptr) nounwind uwtable noinline s
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; X32-SSE1-LABEL: merge_8i16_i16_23u567u9:
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; X32-SSE1: # BB#0:
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi6:
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; X32-SSE1-NEXT: .Lcfi22:
|
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi7:
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; X32-SSE1-NEXT: .Lcfi23:
|
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: .Lcfi8:
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; X32-SSE1-NEXT: .Lcfi24:
|
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; X32-SSE1-NEXT: .cfi_offset %esi, -12
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; X32-SSE1-NEXT: .Lcfi9:
|
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; X32-SSE1-NEXT: .Lcfi25:
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; X32-SSE1-NEXT: .cfi_offset %edi, -8
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
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|
@ -667,24 +897,24 @@ define <16 x i8> @merge_16i8_i8_01u3456789ABCDuF(i8* %ptr) nounwind uwtable noin
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; X32-SSE1-LABEL: merge_16i8_i8_01u3456789ABCDuF:
|
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; X32-SSE1: # BB#0:
|
||||
; X32-SSE1-NEXT: pushl %ebp
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; X32-SSE1-NEXT: .Lcfi10:
|
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; X32-SSE1-NEXT: .Lcfi26:
|
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
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; X32-SSE1-NEXT: pushl %ebx
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||||
; X32-SSE1-NEXT: .Lcfi11:
|
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; X32-SSE1-NEXT: .Lcfi27:
|
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
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; X32-SSE1-NEXT: pushl %edi
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; X32-SSE1-NEXT: .Lcfi12:
|
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; X32-SSE1-NEXT: .Lcfi28:
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; X32-SSE1-NEXT: .cfi_def_cfa_offset 16
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; X32-SSE1-NEXT: pushl %esi
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; X32-SSE1-NEXT: .Lcfi13:
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||||
; X32-SSE1-NEXT: .Lcfi29:
|
||||
; X32-SSE1-NEXT: .cfi_def_cfa_offset 20
|
||||
; X32-SSE1-NEXT: .Lcfi14:
|
||||
; X32-SSE1-NEXT: .Lcfi30:
|
||||
; X32-SSE1-NEXT: .cfi_offset %esi, -20
|
||||
; X32-SSE1-NEXT: .Lcfi15:
|
||||
; X32-SSE1-NEXT: .Lcfi31:
|
||||
; X32-SSE1-NEXT: .cfi_offset %edi, -16
|
||||
; X32-SSE1-NEXT: .Lcfi16:
|
||||
; X32-SSE1-NEXT: .Lcfi32:
|
||||
; X32-SSE1-NEXT: .cfi_offset %ebx, -12
|
||||
; X32-SSE1-NEXT: .Lcfi17:
|
||||
; X32-SSE1-NEXT: .Lcfi33:
|
||||
; X32-SSE1-NEXT: .cfi_offset %ebp, -8
|
||||
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
|
|
@ -917,14 +1147,14 @@ define <2 x i64> @merge_2i64_i64_12_volatile(i64* %ptr) nounwind uwtable noinlin
|
|||
; X32-SSE1-LABEL: merge_2i64_i64_12_volatile:
|
||||
; X32-SSE1: # BB#0:
|
||||
; X32-SSE1-NEXT: pushl %edi
|
||||
; X32-SSE1-NEXT: .Lcfi18:
|
||||
; X32-SSE1-NEXT: .Lcfi34:
|
||||
; X32-SSE1-NEXT: .cfi_def_cfa_offset 8
|
||||
; X32-SSE1-NEXT: pushl %esi
|
||||
; X32-SSE1-NEXT: .Lcfi19:
|
||||
; X32-SSE1-NEXT: .Lcfi35:
|
||||
; X32-SSE1-NEXT: .cfi_def_cfa_offset 12
|
||||
; X32-SSE1-NEXT: .Lcfi20:
|
||||
; X32-SSE1-NEXT: .Lcfi36:
|
||||
; X32-SSE1-NEXT: .cfi_offset %esi, -12
|
||||
; X32-SSE1-NEXT: .Lcfi21:
|
||||
; X32-SSE1-NEXT: .Lcfi37:
|
||||
; X32-SSE1-NEXT: .cfi_offset %edi, -8
|
||||
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %eax
|
||||
; X32-SSE1-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
|
|
|
|||
Loading…
Reference in New Issue