OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

Adjust per revew comments. 

llvm-svn: 42002
This commit is contained in:
Dale Johannesen 2007-09-16 16:51:49 +00:00
parent 2f742085f5
commit 7f724e9b94
1 changed files with 7 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -486,12 +486,7 @@ static SDOperand ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
// double. // double.
MVT::ValueType VT = CFP->getValueType(0); MVT::ValueType VT = CFP->getValueType(0);
bool isDouble = VT == MVT::f64; bool isDouble = VT == MVT::f64;
ConstantFP *LLVMC = ConstantFP::get(VT==MVT::f64 ? Type::DoubleTy : ConstantFP *LLVMC = ConstantFP::get(MVT::getTypeForValueType(VT),
VT==MVT::f32 ? Type::FloatTy :
VT==MVT::f80 ? Type::X86_FP80Ty :
VT==MVT::f128 ? Type::FP128Ty :
VT==MVT::ppcf128 ? Type::PPC_FP128Ty :
Type::VoidTy, // error
CFP->getValueAPF()); CFP->getValueAPF());
if (!UseCP) { if (!UseCP) {
if (VT!=MVT::f64 && VT!=MVT::f32) if (VT!=MVT::f64 && VT!=MVT::f32)
@ -4620,12 +4615,9 @@ ExpandIntToFP(bool isSigned, MVT::ValueType DestTy, SDOperand Source) {
SDOperand FudgeInReg; SDOperand FudgeInReg;
if (DestTy == MVT::f32) if (DestTy == MVT::f32)
FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0); FudgeInReg = DAG.getLoad(MVT::f32, DAG.getEntryNode(), CPIdx, NULL, 0);
else if (DestTy == MVT::f64) else if (MVT::getSizeInBits(DestTy) > MVT::getSizeInBits(MVT::f32))
// FIXME: Avoid the extend by construction the right constantpool? // FIXME: Avoid the extend by construction the right constantpool?
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, DestTy, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32);
else if (DestTy == MVT::f80)
FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f80, DAG.getEntryNode(),
CPIdx, NULL, 0, MVT::f32); CPIdx, NULL, 0, MVT::f32);
else else
assert(0 && "Unexpected conversion"); assert(0 && "Unexpected conversion");
@ -4737,11 +4729,10 @@ SDOperand SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
if (DestVT == MVT::f64) { if (DestVT == MVT::f64) {
// do nothing // do nothing
Result = Sub; Result = Sub;
} else if (DestVT == MVT::f32) { } else if (MVT::getSizeInBits(DestVT) < MVT::getSizeInBits(MVT::f64)) {
// if f32 then cast to f32 Result = DAG.getNode(ISD::FP_ROUND, DestVT, Sub);
Result = DAG.getNode(ISD::FP_ROUND, MVT::f32, Sub); } else if (MVT::getSizeInBits(DestVT) > MVT::getSizeInBits(MVT::f64)) {
} else if (DestVT == MVT::f80) { Result = DAG.getNode(ISD::FP_EXTEND, DestVT, Sub);
Result = DAG.getNode(ISD::FP_EXTEND, MVT::f80, Sub);
} }
return Result; return Result;
} }