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[X86] Address post-commit review from code I accidentally commited in r373136. 

See https://reviews.llvm.org/D68167

llvm-svn: 373245
This commit is contained in:
Craig Topper 2019-09-30 18:43:27 +00:00
parent f0ca10f2ab
commit 8216414fd1
1 changed files with 6 additions and 3 deletions
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9
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -43479,16 +43479,19 @@ static SDValue combineAdd(SDNode *N, SelectionDAG &DAG,
// FIXME: We have the (sub Y, (zext (vXi1 X))) -> (add (sext (vXi1 X)), Y) in
// generic DAG combine without a legal type check, but adding this there
// caused regressions.
if (Subtarget.hasAVX512() && VT.isVector()) {
if (VT.isVector()) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (Op0.getOpcode() == ISD::ZERO_EXTEND &&
Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
Op0.getOperand(0).getValueType().getVectorElementType() == MVT::i1 &&
TLI.isTypeLegal(Op0.getOperand(0).getValueType())) {
SDLoc DL(N);
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op0.getOperand(0));
return DAG.getNode(ISD::SUB, DL, VT, Op1, SExt);
}
if (Op1.getOpcode() == ISD::ZERO_EXTEND &&
Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1) {
Op1.getOperand(0).getValueType().getVectorElementType() == MVT::i1 &&
TLI.isTypeLegal(Op1.getOperand(0).getValueType())) {
SDLoc DL(N);
SDValue SExt = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Op1.getOperand(0));
return DAG.getNode(ISD::SUB, DL, VT, Op0, SExt);