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AVX-512: Fixed encoding of VMOVQ instruction. 

llvm-svn: 191889
This commit is contained in:
Elena Demikhovsky 2013-10-03 12:03:26 +00:00
parent 885d7fa8a4
commit 85aeffaf5c
1 changed files with 3 additions and 3 deletions
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6
llvm/lib/Target/X86/X86InstrAVX512.td
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@ -1227,12 +1227,12 @@ def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W, IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
Requires<[HasAVX512, In64BitMode]>; Requires<[HasAVX512, In64BitMode]>;
def VMOVPQIto64Zmr : I<0x7E, MRMDestMem, (outs), def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
(ins i64mem:$dst, VR128X:$src), (ins i64mem:$dst, VR128X:$src),
"vmovq{z}\t{$src, $dst|$dst, $src}", "vmovq{z}\t{$src, $dst|$dst, $src}",
[(store (extractelt (v2i64 VR128X:$src), (iPTR 0)), [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
addr:$dst)], IIC_SSE_MOVDQ>, addr:$dst)], IIC_SSE_MOVDQ>,
EVEX, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>, EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>; Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
// Move Scalar Single to Double Int // Move Scalar Single to Double Int
@ -1250,7 +1250,7 @@ def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
// Move Quadword Int to Packed Quadword Int // Move Quadword Int to Packed Quadword Int
// //
def VMOVQI2PQIZrm : AVX512SI<0x7E, MRMSrcMem, (outs VR128X:$dst), def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
(ins i64mem:$src), (ins i64mem:$src),
"vmovq{z}\t{$src, $dst|$dst, $src}", "vmovq{z}\t{$src, $dst|$dst, $src}",
[(set VR128X:$dst, [(set VR128X:$dst,