OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

The actual order of parameters in a 2-reg-immediate assembly instructions is 

"rs1, imm, rd": most importantly, rd goes last.

llvm-svn: 6456
This commit is contained in:
Misha Brukman 2003-05-31 04:22:26 +00:00
parent 1656f61b93
commit 87cbd97710
1 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
llvm/lib/Target/Sparc/SparcV9_F3.td
View File

@ -56,17 +56,29 @@ class F3_rs1rs2 : F3_rs1 {
set Inst{4-0} = rs2; set Inst{4-0} = rs2;
} }
// F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
class F3_rs1rs2rd : F3_rs1rs2 {
bits<5> rd;
set Inst{29-25} = rd;
set Inst{4-0} = rs2;
}
// F3_rs1simm13 - Common class of instructions that only have rs1 and simm13 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
class F3_rs1simm13 : F3_rs1 { class F3_rs1simm13 : F3_rs1 {
bits<13> simm13; bits<13> simm13;
set Inst{12-0} = simm13; set Inst{12-0} = simm13;
} }
class F3_rs1simm13rd : F3_rs1simm13 {
bits<5> rd;
set Inst{29-25} = rd;
}
// Specific F3 classes... // Specific F3 classes...
// //
class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 { class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
set op = opVal; set op = opVal;
set op3 = op3val; set op3 = op3val;
set Name = name; set Name = name;
@ -74,13 +86,33 @@ class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
//set Inst{12-5} = dontcare; //set Inst{12-5} = dontcare;
} }
class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 { class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
set op = opVal; set op = opVal;
set op3 = op3val; set op3 = op3val;
set Name = name; set Name = name;
set Inst{13} = 1; // i field = 1 set Inst{13} = 1; // i field = 1
} }
#if 0
// The ordering is actually incorrect in these: in the assemble syntax,
// rd appears last!
class F3_1a<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
set op = opVal;
set op3 = op3val;
set Name = name;
set Inst{13} = 0; // i field = 0
//set Inst{12-5} = dontcare;
}
class F3_2a<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
set op = opVal;
set op3 = op3val;
set Name = name;
set Inst{13} = 1; // i field = 1
}
#endif
class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 { class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
set op = opVal; set op = opVal;
set op3 = op3val; set op3 = op3val;