[GlobalISel] Enforce G_ASSERT_ALIGN to have a valid alignment > 0.
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60990d9042
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@ -39,7 +39,7 @@ Align GISelKnownBits::computeKnownAlignment(Register R, unsigned Depth) {
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return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
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return computeKnownAlignment(MI->getOperand(1).getReg(), Depth);
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case TargetOpcode::G_ASSERT_ALIGN: {
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case TargetOpcode::G_ASSERT_ALIGN: {
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// TODO: Min with source
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// TODO: Min with source
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return Align(std::max(int64_t(1), MI->getOperand(2).getImm()));
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return Align(MI->getOperand(2).getImm());
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}
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}
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case TargetOpcode::G_FRAME_INDEX: {
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case TargetOpcode::G_FRAME_INDEX: {
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int FrameIdx = MI->getOperand(1).getIndex();
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int FrameIdx = MI->getOperand(1).getIndex();
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@ -471,10 +471,7 @@ void GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
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break;
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break;
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}
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}
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case TargetOpcode::G_ASSERT_ALIGN: {
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case TargetOpcode::G_ASSERT_ALIGN: {
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int64_t Align = MI.getOperand(2).getImm();
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int64_t LogOfAlign = Log2_64(MI.getOperand(2).getImm());
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if (Align == 0)
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break;
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int64_t LogOfAlign = Log2_64(Align);
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// TODO: Should use maximum with source
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// TODO: Should use maximum with source
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// If a node is guaranteed to be aligned, set low zero bits accordingly as
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// If a node is guaranteed to be aligned, set low zero bits accordingly as
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@ -1725,6 +1725,11 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
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}
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}
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break;
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break;
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}
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}
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case TargetOpcode::G_ASSERT_ALIGN: {
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if (MI->getOperand(2).getImm() < 1)
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report("alignment immediate must be >= 1", MI);
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break;
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}
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default:
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default:
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break;
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break;
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}
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}
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@ -0,0 +1,17 @@
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#RUN: not --crash llc -march=aarch64 -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: aarch64-registered-target
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---
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name: test_assert_align
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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liveins:
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body: |
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bb.0:
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liveins: $x0, $q0
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%ptr:_(p0) = COPY $x0
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; CHECK: Bad machine code: alignment immediate must be >= 1
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%v:_(s32) = G_ASSERT_ALIGN %ptr:_(p0), 0
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@ -1923,9 +1923,6 @@ TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
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%val:_(s64) = COPY $vgpr0_vgpr1
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%val:_(s64) = COPY $vgpr0_vgpr1
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%ptrval:_(p1) = COPY $vgpr0_vgpr1
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%ptrval:_(p1) = COPY $vgpr0_vgpr1
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%assert_align0:_(s64) = G_ASSERT_ALIGN %val, 0
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%copy_assert_align0:_(s64) = COPY %assert_align0
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%assert_align1:_(s64) = G_ASSERT_ALIGN %val, 1
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%assert_align1:_(s64) = G_ASSERT_ALIGN %val, 1
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%copy_assert_align1:_(s64) = COPY %assert_align1
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%copy_assert_align1:_(s64) = COPY %assert_align1
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@ -1962,17 +1959,11 @@ TEST_F(AMDGPUGISelMITest, TestKnownBitsAssertAlign) {
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};
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};
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const unsigned NumSetupCopies = 5;
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const unsigned NumSetupCopies = 5;
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// Check zero align specially.
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CheckBits(1, NumSetupCopies);
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Res = GetKB(NumSetupCopies);
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CheckBits(2, NumSetupCopies + 1);
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EXPECT_EQ(0u, Res.Zero.countTrailingOnes());
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CheckBits(3, NumSetupCopies + 2);
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EXPECT_EQ(64u, Res.One.countTrailingZeros());
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CheckBits(4, NumSetupCopies + 3);
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EXPECT_EQ(Align(1), Info.computeKnownAlignment(Copies[5]));
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CheckBits(5, NumSetupCopies + 4);
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CheckBits(1, NumSetupCopies + 1);
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CheckBits(2, NumSetupCopies + 2);
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CheckBits(3, NumSetupCopies + 3);
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CheckBits(4, NumSetupCopies + 4);
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CheckBits(5, NumSetupCopies + 5);
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}
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}
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TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
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TEST_F(AArch64GISelMITest, TestKnownBitsUADDO) {
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