[AMDGPU] Change FLAT SADDR to VADDR form in moveToVALU
Instead of legalizing saddr operand with a readfirstlane when address is moved from SGPR to VGPR we can just change the opcode. Differential Revision: https://reviews.llvm.org/D101405
This commit is contained in:
Stanislav Mekhanoshin
parent
a27ca15dd0
commit
89a94be16b
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@ -5012,6 +5012,63 @@ void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
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}
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}
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bool SIInstrInfo::moveFlatAddrToVGPR(MachineInstr &Inst) const {
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unsigned Opc = Inst.getOpcode();
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int OldSAddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
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if (OldSAddrIdx < 0)
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return false;
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assert(isSegmentSpecificFLAT(Inst));
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int NewOpc = AMDGPU::getGlobalVaddrOp(Opc);
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if (NewOpc < 0)
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return false;
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MachineRegisterInfo &MRI = Inst.getMF()->getRegInfo();
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MachineOperand &SAddr = Inst.getOperand(OldSAddrIdx);
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if (RI.isSGPRReg(MRI, SAddr.getReg()))
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return false;
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int NewVAddrIdx = AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vaddr);
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if (NewVAddrIdx < 0)
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return false;
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int OldVAddrIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr);
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assert(OldVAddrIdx >= 0);
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// Check vaddr, it shall be zero
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MachineOperand &VAddr = Inst.getOperand(OldVAddrIdx);
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MachineInstr *VAddrDef = MRI.getUniqueVRegDef(VAddr.getReg());
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if (!VAddrDef || VAddrDef->getOpcode() != AMDGPU::V_MOV_B32_e32 ||
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!VAddrDef->getOperand(1).isImm() || VAddrDef->getOperand(1).getImm() != 0)
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return false;
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const MCInstrDesc &NewDesc = get(NewOpc);
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Inst.setDesc(NewDesc);
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// Callers expect interator to be valid after this call, so modify the
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// instruction in place.
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if (OldVAddrIdx == NewVAddrIdx) {
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MachineOperand &NewVAddr = Inst.getOperand(NewVAddrIdx);
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// Clear use list from the old vaddr holding a zero register.
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MRI.removeRegOperandFromUseList(&NewVAddr);
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MRI.moveOperands(&NewVAddr, &SAddr, 1);
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Inst.RemoveOperand(OldSAddrIdx);
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// Update the use list with the pointer we have just moved from vaddr to
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// saddr poisition. Otherwise new vaddr will be missing from the use list.
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MRI.removeRegOperandFromUseList(&NewVAddr);
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MRI.addRegOperandToUseList(&NewVAddr);
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} else {
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assert(OldSAddrIdx == NewVAddrIdx);
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Inst.RemoveOperand(OldVAddrIdx);
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}
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if (MRI.use_nodbg_empty(VAddrDef->getOperand(0).getReg()))
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VAddrDef->eraseFromParent();
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return true;
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}
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// FIXME: Remove this when SelectionDAG is obsoleted.
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void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
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MachineInstr &MI) const {
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@ -5024,6 +5081,9 @@ void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
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if (!SAddr || RI.isSGPRClass(MRI.getRegClass(SAddr->getReg())))
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return;
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if (moveFlatAddrToVGPR(MI))
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return;
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Register ToSGPR = readlaneVGPRToSGPR(SAddr->getReg(), MI, MRI);
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SAddr->setReg(ToSGPR);
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}
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@ -946,6 +946,10 @@ public:
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MachineBasicBlock *
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legalizeOperands(MachineInstr &MI, MachineDominatorTree *MDT = nullptr) const;
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/// Change SADDR form of a FLAT \p Inst to its VADDR form if saddr operand
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/// was moved to VGPR. \returns true if succeeded.
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bool moveFlatAddrToVGPR(MachineInstr &Inst) const;
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/// Replace this instruction's opcode with the equivalent VALU
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/// opcode. This function will also move the users of \p MI to the
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/// VALU if necessary. If present, \p MDT is updated.
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@ -1198,9 +1202,16 @@ namespace AMDGPU {
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LLVM_READONLY
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int getSOPKOp(uint16_t Opcode);
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/// \returns SADDR form of a FLAT Global instruction given an \p Opcode
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/// of a VADDR form.
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LLVM_READONLY
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int getGlobalSaddrOp(uint16_t Opcode);
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/// \returns VADDR form of a FLAT Global instruction given an \p Opcode
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/// of a SADDR form.
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LLVM_READONLY
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int getGlobalVaddrOp(uint16_t Opcode);
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LLVM_READONLY
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int getVCMPXNoSDstOp(uint16_t Opcode);
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@ -2505,6 +2505,15 @@ def getGlobalSaddrOp : InstrMapping {
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let ValueCols = [["1"]];
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}
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// Maps a GLOBAL SADDR to its VADDR form.
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def getGlobalVaddrOp : InstrMapping {
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let FilterClass = "GlobalSaddrTable";
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let RowFields = ["SaddrOp"];
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let ColFields = ["IsSaddr"];
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let KeyCol = ["1"];
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let ValueCols = [["0"]];
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}
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// Maps a v_cmpx opcode with sdst to opcode without sdst.
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def getVCMPXNoSDstOp : InstrMapping {
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let FilterClass = "VCMPXNoSDstTable";
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@ -0,0 +1,33 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; The first load produces address in a VGPR which is used in address calculation
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; of the second load (one inside the loop). The value is uniform and the inner
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; load correctly selected to use SADDR form, however the address is promoted to
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; vector registers because it all starts with a VGPR produced by the entry block
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; load.
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;
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; Check that we are changing SADDR form of a load to VADDR and do not have to use
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; readfirstlane instructions to move address from VGPRs into SGPRs.
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; GCN-LABEL: {{^}}test_move_load_address_to_vgpr:
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; GCN: BB{{[0-9]+}}_1:
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; GCN-NOT: v_readfirstlane_b32
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; GCN: global_load_dword v{{[0-9]+}}, v[{{[0-9:]+}}], off glc
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define amdgpu_kernel void @test_move_load_address_to_vgpr(i32 addrspace(1)* nocapture %arg) {
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bb:
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%i1 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 0
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%i2 = load volatile i32, i32 addrspace(1)* %i1, align 4
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]
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%i4 = zext i32 %i to i64
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%i5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %i4
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%i6 = load volatile i32, i32 addrspace(1)* %i5, align 4
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%i8 = add nuw nsw i32 %i, 1
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%i9 = icmp eq i32 %i8, 256
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br i1 %i9, label %bb2, label %bb3
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}
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@ -0,0 +1,413 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
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---
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name: global_load_saddr_to_valu
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: global_load_saddr_to_valu
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: bb.1:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN: [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI]], 0, 0, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec
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; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
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; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.2:
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; GCN: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
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%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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---
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name: global_load_saddr_to_valu_non_zero_vaddr
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: global_load_saddr_to_valu_non_zero_vaddr
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: bb.1:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
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; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec
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; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
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; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.2:
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; GCN: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
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%3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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---
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name: global_load_saddr_to_valu_undef_vaddr
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: global_load_saddr_to_valu_undef_vaddr
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: bb.1:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
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; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
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; GCN: [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec
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; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
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; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.2:
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; GCN: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
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%4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, undef %3:vgpr_32, 0, 0, implicit $exec
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%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
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S_CMP_LG_U64 %2, 0, implicit-def $scc
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S_CBRANCH_SCC1 %bb.1, implicit $scc
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bb.2:
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S_ENDPGM 0
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...
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---
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name: global_store_saddr_to_valu
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: global_store_saddr_to_valu
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; GCN: bb.0:
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; GCN: successors: %bb.1(0x80000000)
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; GCN: liveins: $vgpr0_vgpr1
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; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
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; GCN: bb.1:
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; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: GLOBAL_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
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; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
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; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
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; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
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; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
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; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec
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; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
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; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
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; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
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; GCN: bb.2:
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; GCN: S_ENDPGM 0
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bb.0:
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liveins: $vgpr0_vgpr1
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%0:sreg_64 = COPY $vgpr0_vgpr1
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bb.1:
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%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
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%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%4:vgpr_32 = IMPLICIT_DEF
|
||||
GLOBAL_STORE_DWORD_SADDR %3, %4, %1, 0, 0, implicit $exec
|
||||
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U64 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: global_addtid_load_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: global_addtid_load_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0_vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
|
||||
; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
|
||||
; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
|
||||
; GCN: [[GLOBAL_LOAD_DWORD_ADDTID_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR [[REG_SEQUENCE]], 0, 0, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
|
||||
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
|
||||
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1
|
||||
%0:sreg_64 = COPY $vgpr0_vgpr1
|
||||
|
||||
bb.1:
|
||||
%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
|
||||
%4:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR %1, 0, 0, implicit $exec
|
||||
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U64 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: global_store_addtid_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: global_store_addtid_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0_vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
|
||||
; GCN: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
|
||||
; GCN: GLOBAL_STORE_DWORD_ADDTID_SADDR [[DEF]], [[REG_SEQUENCE]], 0, 0, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
|
||||
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
|
||||
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE1]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1
|
||||
%0:sreg_64 = COPY $vgpr0_vgpr1
|
||||
|
||||
bb.1:
|
||||
%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
|
||||
%4:vgpr_32 = IMPLICIT_DEF
|
||||
GLOBAL_STORE_DWORD_ADDTID_SADDR %4, %1, 0, 0, implicit $exec
|
||||
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U64 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: global_atomic_noret_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: global_atomic_noret_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0_vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
|
||||
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GCN: GLOBAL_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
|
||||
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
|
||||
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1
|
||||
%0:sreg_64 = COPY $vgpr0_vgpr1
|
||||
|
||||
bb.1:
|
||||
%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
|
||||
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
GLOBAL_ATOMIC_ADD_SADDR %3, %3, %1, 0, 0, implicit $exec
|
||||
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U64 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: global_atomic_rtn_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: global_atomic_rtn_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0_vgpr1
|
||||
; GCN: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
|
||||
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GCN: [[GLOBAL_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
|
||||
; GCN: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
|
||||
; GCN: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
|
||||
; GCN: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
|
||||
; GCN: V_CMP_NE_U64_e32 0, [[REG_SEQUENCE]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1
|
||||
%0:sreg_64 = COPY $vgpr0_vgpr1
|
||||
|
||||
bb.1:
|
||||
%1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
|
||||
%3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
%4:vgpr_32 = GLOBAL_ATOMIC_ADD_SADDR_RTN %3, %3, %1, 0, 0, implicit $exec
|
||||
%2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U64 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: scratch_load_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: scratch_load_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
|
||||
; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]], implicit $exec
|
||||
; GCN: [[SCRATCH_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR [[V_READFIRSTLANE_B32_]], 0, 0, implicit $exec, implicit $flat_scr
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
|
||||
; GCN: V_CMP_NE_U32_e32 0, [[V_AND_B32_e64_]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
%0:sgpr_32 = COPY $vgpr0
|
||||
|
||||
bb.1:
|
||||
%1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
|
||||
%4:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U32 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
|
||||
---
|
||||
name: scratch_store_saddr_to_valu
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
; GCN-LABEL: name: scratch_store_saddr_to_valu
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: liveins: $vgpr0
|
||||
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
||||
; GCN: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]], implicit $exec
|
||||
; GCN: SCRATCH_STORE_DWORD_SADDR [[DEF]], [[V_READFIRSTLANE_B32_]], 0, 0, implicit $exec, implicit $flat_scr
|
||||
; GCN: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
|
||||
; GCN: V_CMP_NE_U32_e32 0, [[V_AND_B32_e64_]], implicit-def $vcc, implicit $exec
|
||||
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
|
||||
; GCN: $vcc = S_AND_B64 $exec, $vcc, implicit-def $scc
|
||||
; GCN: S_CBRANCH_VCCNZ %bb.1, implicit $vcc
|
||||
; GCN: bb.2:
|
||||
; GCN: S_ENDPGM 0
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
%0:sgpr_32 = COPY $vgpr0
|
||||
|
||||
bb.1:
|
||||
%1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
|
||||
%4:vgpr_32 = IMPLICIT_DEF
|
||||
SCRATCH_STORE_DWORD_SADDR %4, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
|
||||
S_CMP_LG_U32 %2, 0, implicit-def $scc
|
||||
S_CBRANCH_SCC1 %bb.1, implicit $scc
|
||||
|
||||
bb.2:
|
||||
S_ENDPGM 0
|
||||
...
|
||||
Loading…
Reference in New Issue