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support for larger calls 

llvm-svn: 19932
This commit is contained in:
Andrew Lenharth 2005-01-30 00:35:27 +00:00
parent 79a85fada1
commit 918a29fc51
2 changed files with 125 additions and 99 deletions
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62
llvm/lib/Target/Alpha/AlphaISelPattern.cpp
View File

@ -27,6 +27,7 @@
#include "llvm/Support/MathExtras.h" #include "llvm/Support/MathExtras.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include <set> #include <set>
#include <algorithm>
using namespace llvm; using namespace llvm;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -138,34 +139,42 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I) for (Function::aiterator I = F.abegin(), E = F.aend(); I != E; ++I)
{ {
SDOperand newroot, argt; SDOperand newroot, argt;
++count; if (count < 6) {
assert(count <= 6 && "More than 6 args not supported");
switch (getValueType(I->getType())) { switch (getValueType(I->getType())) {
default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort(); default: std::cerr << "Unknown Type " << getValueType(I->getType()) << "\n"; abort();
case MVT::f64: case MVT::f64:
case MVT::f32: case MVT::f32:
BuildMI(&BB, Alpha::IDEF, 0, args_float[count - 1]); BuildMI(&BB, Alpha::IDEF, 0, args_float[count]);
argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType())))); argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(getValueType(I->getType()))));
argPreg.push_back(args_float[count - 1]); argPreg.push_back(args_float[count]);
argOpc.push_back(Alpha::CPYS); argOpc.push_back(Alpha::CPYS);
newroot = DAG.getCopyFromReg(argVreg[count-1], getValueType(I->getType()), DAG.getRoot()); newroot = DAG.getCopyFromReg(argVreg[count], getValueType(I->getType()), DAG.getRoot());
break; break;
case MVT::i1: case MVT::i1:
case MVT::i8: case MVT::i8:
case MVT::i16: case MVT::i16:
case MVT::i32: case MVT::i32:
case MVT::i64: case MVT::i64:
BuildMI(&BB, Alpha::IDEF, 0, args_int[count - 1]); BuildMI(&BB, Alpha::IDEF, 0, args_int[count]);
argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64))); argVreg.push_back(MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)));
argPreg.push_back(args_int[count - 1]); argPreg.push_back(args_int[count]);
argOpc.push_back(Alpha::BIS); argOpc.push_back(Alpha::BIS);
argt = newroot = DAG.getCopyFromReg(argVreg[count-1], MVT::i64, DAG.getRoot()); argt = newroot = DAG.getCopyFromReg(argVreg[count], MVT::i64, DAG.getRoot());
if (getValueType(I->getType()) != MVT::i64) if (getValueType(I->getType()) != MVT::i64)
argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot); argt = DAG.getNode(ISD::TRUNCATE, getValueType(I->getType()), newroot);
break; break;
} }
} else { //more args
// Create the frame index object for this incoming parameter...
int FI = MFI->CreateFixedObject(8, 8 * (count - 6));
// Create the SelectionDAG nodes corresponding to a load from this parameter
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
argt = newroot = DAG.getLoad(getValueType(I->getType()), DAG.getEntryNode(), FIN);
}
DAG.setRoot(newroot.getValue(1)); DAG.setRoot(newroot.getValue(1));
ArgValues.push_back(argt); ArgValues.push_back(argt);
++count;
} }
BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29); BuildMI(&BB, Alpha::IDEF, 0, Alpha::R29);
@ -181,6 +190,9 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain,
const Type *RetTy, SDOperand Callee, const Type *RetTy, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) { ArgListTy &Args, SelectionDAG &DAG) {
int NumBytes = 0; int NumBytes = 0;
if (Args.size() > 6)
NumBytes = (Args.size() - 6) * 8;
Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain, Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
DAG.getConstant(NumBytes, getPointerTy())); DAG.getConstant(NumBytes, getPointerTy()));
std::vector<SDOperand> args_to_use; std::vector<SDOperand> args_to_use;
@ -404,9 +416,9 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
//STL LDS //STL LDS
//STQ LDT //STQ LDT
Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL; Opc = DestType == MVT::f64 ? Alpha::STQ : Alpha::STL;
BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx); BuildMI(BB, Opc, 2).addReg(Tmp1).addFrameIndex(FrameIdx).addReg(Alpha::F31);
Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS; Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx); BuildMI(BB, Opc, 1, Result).addFrameIndex(FrameIdx).addReg(Alpha::F31);
//The easy way: doesn't work //The easy way: doesn't work
// //so these instructions are not supported on ev56 // //so these instructions are not supported on ev56
@ -467,7 +479,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
case ISD::FrameIndex: case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex(); Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1); BuildMI(BB, Alpha::LDA, 2, Result).addFrameIndex(Tmp1).addReg(Alpha::F31);
return Result; return Result;
case ISD::EXTLOAD: case ISD::EXTLOAD:
@ -576,7 +588,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
for(int i = 2, e = Node->getNumOperands(); i < e; ++i) for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
argvregs.push_back(SelectExpr(N.getOperand(i))); argvregs.push_back(SelectExpr(N.getOperand(i)));
for(int i = 0, e = argvregs.size(); i < e; ++i) //in reg args
for(int i = 0, e = std::min(6, (int)argvregs.size()); i < e; ++i)
{ {
unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18, unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
Alpha::R19, Alpha::R20, Alpha::R21}; Alpha::R19, Alpha::R20, Alpha::R21};
@ -600,7 +613,30 @@ unsigned ISel::SelectExpr(SDOperand N) {
BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]); BuildMI(BB, Alpha::CPYS, 2, args_float[i]).addReg(argvregs[i]).addReg(argvregs[i]);
break; break;
} }
}
//in mem args
for (int i = 6, e = argvregs.size(); i < e; ++i)
{
switch(N.getOperand(i+2).getValueType()) {
default:
Node->dump();
N.getOperand(i).Val->dump();
std::cerr << "Type for " << i << " is: " << N.getOperand(i+2).getValueType() << "\n";
assert(0 && "Unknown value type for call");
case MVT::i1:
case MVT::i8:
case MVT::i16:
case MVT::i32:
case MVT::i64:
BuildMI(BB, Alpha::STQ, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
break;
case MVT::f32:
BuildMI(BB, Alpha::STS, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
break;
case MVT::f64:
BuildMI(BB, Alpha::STT, 3).addReg(argvregs[i]).addImm((i - 6) * 8).addReg(Alpha::R30);
break;
}
} }
//build the right kind of call //build the right kind of call
if (GlobalAddressSDNode *GASD = if (GlobalAddressSDNode *GASD =

76
llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -49,7 +49,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx) const { unsigned SrcReg, int FrameIdx) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx); BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
// assert(0 && "TODO"); // assert(0 && "TODO");
} }
@ -59,7 +59,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
unsigned DestReg, int FrameIdx) const{ unsigned DestReg, int FrameIdx) const{
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0, DestReg); //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx); BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
// assert(0 && "TODO"); // assert(0 && "TODO");
} }
@ -128,53 +128,35 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
void void
AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
assert(0 && "TODO"); unsigned i = 0;
// unsigned i = 0; MachineInstr &MI = *II;
// MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent();
// MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent();
// MachineFunction &MF = *MBB.getParent();
// while (!MI.getOperand(i).isFrameIndex()) { while (!MI.getOperand(i).isFrameIndex()) {
// ++i; ++i;
// assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
// } }
// int FrameIndex = MI.getOperand(i).getFrameIndex(); int FrameIndex = MI.getOperand(i).getFrameIndex();
// // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). // Add the base register of R30 (SP) or R15 (FP).
// MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1); MI.SetMachineOperandReg(i + 1, hasFP(MF) ? Alpha::R15 : Alpha::R30);
// // Take into account whether it's an add or mem instruction // Now add the frame object offset to the offset from r1.
// unsigned OffIdx = (i == 2) ? 1 : 2; int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
// // Now add the frame object offset to the offset from r1. // If we're not using a Frame Pointer that has been set to the value of the
// int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + // SP before having the stack size subtracted from it, then add the stack size
// MI.getOperand(OffIdx).getImmedValue(); // to Offset to get the correct offset.
Offset += MF.getFrameInfo()->getStackSize();
// // If we're not using a Frame Pointer that has been set to the value of the if (Offset > 32767 || Offset < -32768) {
// // SP before having the stack size subtracted from it, then add the stack size std::cerr << "Offset needs to be " << Offset << "\n";
// // to Offset to get the correct offset. assert(0 && "stack too big");
// Offset += MF.getFrameInfo()->getStackSize(); } else {
MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset);
// if (Offset > 32767 || Offset < -32768) { }
// // Insert a set of r0 with the full offset value before the ld, st, or add
// MachineBasicBlock *MBB = MI.getParent();
// MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
// MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
// .addImm(Offset));
// // convert into indexed form of the instruction
// // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
// // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
// unsigned NewOpcode =
// const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
// assert(NewOpcode && "No indexed form of load or store available!");
// MI.setOpcode(NewOpcode);
// MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
// MI.SetMachineOperandReg(2, PPC::R0);
// } else {
// MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
// Offset);
// }
} }
@ -191,6 +173,14 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const {
// Get the number of bytes to allocate from the FrameInfo // Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize(); unsigned NumBytes = MFI->getStackSize();
if (MFI->hasCalls()) {
// We reserve argument space for call sites in the function immediately on
// entry to the current function. This eliminates the need for add/sub
// brackets around call sites.
NumBytes += MFI->getMaxCallFrameSize();
std::cerr << "Added " << MFI->getMaxCallFrameSize() << " to the stack due to calls\n";
}
// Do we need to allocate space on the stack? // Do we need to allocate space on the stack?
if (NumBytes == 0) return; if (NumBytes == 0) return;