[AArch64][GlobalISel] Emit G_ASSERT_SEXT for SExt parameters in CallLowering
Similar to how we emit G_ASSERT_ZEXT when we have CCValAssign::LocInfo::ZExt. This will allow us to combine away some redundant sign extends. Example: https://godbolt.org/z/cTbKvr Differential Revision: https://reviews.llvm.org/D96915
This commit is contained in:
Jessica Paquette
parent
7d1397f7ad
commit
95d13c01ec
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@ -83,7 +83,15 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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NarrowTy.getSizeInBits()));
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break;
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}
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::SExt: {
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auto WideTy = LLT{VA.getLocVT()};
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auto NarrowTy = MRI.getType(ValVReg);
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MIRBuilder.buildTrunc(ValVReg,
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MIRBuilder.buildAssertSExt(
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WideTy, MIRBuilder.buildCopy(WideTy, PhysReg),
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NarrowTy.getSizeInBits()));
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break;
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}
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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@ -104,16 +112,28 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
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MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
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MemSize, inferAlignFromPtrInfo(MF, MPO));
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const LLT LocVT = LLT{VA.getLocVT()};
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if (VA.getLocInfo() == CCValAssign::LocInfo::ZExt &&
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RegTy.getScalarSizeInBits() < LocVT.getScalarSizeInBits()) {
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// We know the parameter is zero-extended. Perform a load into LocVT, and
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// use G_ASSERT_ZEXT to communicate that this was zero-extended from the
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// parameter type. Move down to the parameter type using G_TRUNC.
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MIRBuilder.buildTrunc(ValVReg,
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MIRBuilder.buildAssertZExt(
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LocVT, MIRBuilder.buildLoad(LocVT, Addr, *MMO),
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RegTy.getScalarSizeInBits()));
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return;
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if (RegTy.getScalarSizeInBits() < LocVT.getScalarSizeInBits()) {
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auto LocInfo = VA.getLocInfo();
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if (LocInfo == CCValAssign::LocInfo::ZExt) {
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// We know the parameter is zero-extended. Perform a load into LocVT,
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// and use G_ASSERT_ZEXT to communicate that this was zero-extended from
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// the parameter type. Move down to the parameter type using G_TRUNC.
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MIRBuilder.buildTrunc(
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ValVReg, MIRBuilder.buildAssertZExt(
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LocVT, MIRBuilder.buildLoad(LocVT, Addr, *MMO),
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RegTy.getScalarSizeInBits()));
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return;
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}
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if (LocInfo == CCValAssign::LocInfo::SExt) {
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// Same as the ZExt case, but use G_ASSERT_SEXT instead.
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MIRBuilder.buildTrunc(
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ValVReg, MIRBuilder.buildAssertSExt(
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LocVT, MIRBuilder.buildLoad(LocVT, Addr, *MMO),
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RegTy.getScalarSizeInBits()));
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return;
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}
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}
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// No extension information, or no extension necessary. Load into the
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@ -0,0 +1,118 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=aarch64 -global-isel -stop-after=irtranslator -verify-machineinstrs -o - %s | FileCheck %s
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; Verify that we generate G_ASSERT_SEXT for signext parameters.
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define i8 @signext_param_i8(i8 signext %x) {
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; CHECK-LABEL: name: signext_param_i8
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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ret i8 %x
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}
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define i8 @no_signext_param(i8 %x) {
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; CHECK-LABEL: name: no_signext_param
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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ret i8 %x
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}
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; Don't need G_ASSERT_SEXT here. The sizes match.
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define i32 @signext_param_i32(i32 signext %x) {
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; CHECK-LABEL: name: signext_param_i32
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $w0
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: $w0 = COPY [[COPY]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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ret i32 %x
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}
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; Zeroext param is passed on the stack. We should still get a G_ASSERT_SEXT.
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define i32 @signext_param_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
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; CHECK-LABEL: name: signext_param_stack
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 16)
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; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0, align 8)
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; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 1
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; CHECK: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ASSERT_SEXT]](s32)
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s1)
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; CHECK: $w0 = COPY [[ZEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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i64 %g, i64 %h, i64 %i, i1 signext %j) {
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%v = zext i1 %j to i32
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ret i32 %v
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}
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; The signext parameter is a s32, so there's no extension required.
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define i32 @dont_need_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
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; CHECK-LABEL: name: dont_need_assert_zext_stack
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 16)
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; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.0, align 8)
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; CHECK: $w0 = COPY [[LOAD1]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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i64 %f, i64 %g, i64 %h, i64 %i,
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i32 signext %j) {
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ret i32 %j
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}
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; s8 requires extension to s32, so we should get a G_ASSERT_SEXT here.
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define i8 @s8_assert_zext_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
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; CHECK-LABEL: name: s8_assert_zext_stack
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
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; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
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; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
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; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
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; CHECK: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
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; CHECK: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
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; CHECK: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 8 from %fixed-stack.1, align 16)
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; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0, align 8)
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; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC]](s8)
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; CHECK: $w0 = COPY [[ANYEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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i64 %f, i64 %g, i64 %h, i64 %i,
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i8 signext %j) {
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ret i8 %j
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}
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@ -5,13 +5,18 @@
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; CHECK: fixedStack:
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; CHECK-DAG: - { id: [[STACK0:[0-9]+]], type: default, offset: 0, size: 1,
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; CHECK-DAG: - { id: [[STACK8:[0-9]+]], type: default, offset: 1, size: 1,
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; CHECK: [[LHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK0]]
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; CHECK: [[LHS:%[0-9]+]]:_(s8) = G_LOAD [[LHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK0]], align 16)
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; CHECK: [[RHS_ADDR:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[STACK8]]
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; CHECK: [[RHS:%[0-9]+]]:_(s8) = G_LOAD [[RHS_ADDR]](p0) :: (invariant load 1 from %fixed-stack.[[STACK8]])
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; CHECK: [[SUM:%[0-9]+]]:_(s8) = G_ADD [[LHS]], [[RHS]]
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; CHECK: [[SUM32:%[0-9]+]]:_(s32) = G_SEXT [[SUM]](s8)
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; CHECK: $w0 = COPY [[SUM32]](s32)
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; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
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; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.1, align 16)
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; CHECK: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD]], 8
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT]](s32)
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; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
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; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.0)
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; CHECK: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[LOAD1]], 8
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ASSERT_SEXT1]](s32)
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; CHECK: [[ADD:%[0-9]+]]:_(s8) = G_ADD [[TRUNC]], [[TRUNC1]]
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; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[ADD]](s8)
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; CHECK: $w0 = COPY [[SEXT]](s32)
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; CHECK: RET_ReallyLR implicit $w0
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define signext i8 @test_stack_slots([8 x i64], i8 signext %lhs, i8 signext %rhs) {
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%sum = add i8 %lhs, %rhs
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ret i8 %sum
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