[AArch64] Lower 2-CC FCCMPs (one/ueq) using AND'ed CCs.
The current behavior is incorrect, as the two CCs returned by
changeFPCCToAArch64CC, intended to be OR'ed, are instead used
in an AND ccmp chain.
Consider:
define i32 @t(float %a, float %b, float %c, float %d, i32 %e, i32 %f) {
%cc1 = fcmp one float %a, %b
%cc2 = fcmp olt float %c, %d
%and = and i1 %cc1, %cc2
%r = select i1 %and, i32 %e, i32 %f
ret i32 %r
}
Assuming (%a < %b) and (%c < %d); we used to do:
fcmp s0, s1 # nzcv <- 1000
orr w8, wzr, #0x1 # w8 <- 1
csel w9, w8, wzr, mi # w9 <- 1
csel w8, w8, w9, gt # w8 <- 1
fcmp s2, s3 # nzcv <- 1000
cset w9, mi # w9 <- 1
tst w8, w9 # (w8 & w9) == 1, so: nzcv <- 0000
csel w0, w0, w1, ne # w0 <- w0
We now do:
fcmp s2, s3 # nzcv <- 1000
fccmp s0, s1, #0, mi # mi, so: nzcv <- 1000
fccmp s0, s1, #8, le # !le, so: nzcv <- 1000
csel w0, w0, w1, pl # !pl, so: w0 <- w1
In other words, we transformed:
(c < d) && ((a < b) || (a > b))
into:
(c < d) && (a u>= b) && (a u<= b)
whereas, per De Morgan's, we wanted:
(c < d) && !((a u>= b) && (a u<= b))
Note that this problem doesn't occur in the test-suite.
changeFPCCToAArch64CC produces disjunct CCs; here, one -> mi/gt.
We can't represent that in the fccmp chain; it can't express
arbitrary OR sequences, as one comment explains:
In general we can create code for arbitrary "... (and (and A B) C)"
sequences. We can also implement some "or" expressions, because
"(or A B)" is equivalent to "not (and (not A) (not B))" and we can
implement some negation operations. [...] However there is no way
to negate the result of a partial sequence.
Instead, introduce changeFPCCToANDAArch64CC, which produces the
conjunct cond codes:
- (a one b)
== ((a olt b) || (a ogt b))
== ((a ord b) && (a une b))
- (a ueq b)
== ((a uno b) || (a oeq b))
== ((a ule b) && (a uge b))
Note that, at first, one might think that, when PushNegate is true,
we should use the disjunct CCs, in effect doing:
(a || b)
= !(!a && !(b))
= !(!a && !(b1 || b2)) <- changeFPCCToAArch64CC(b, b1, b2)
= !(!a && !b1 && !b2)
However, we can take advantage of the fact that the CC is already
negated, which lets us avoid special-casing PushNegate and doing
the simpler to reason about:
(a || b)
= !(!a && (!b))
= !(!a && (b1 && b2)) <- changeFPCCToANDAArch64CC(!b, b1, b2)
= !(!a && b1 && b2)
This makes both emitConditionalCompare cases behave identically,
and produces correct ccmp sequences for the 2-CC fcmps.
llvm-svn: 258533
This commit is contained in:
Ahmed Bougacha
parent
6345b9ecfa
commit
99209b90a4
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@ -1135,6 +1135,35 @@ static void changeFPCCToAArch64CC(ISD::CondCode CC,
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}
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}
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/// Convert a DAG fp condition code to an AArch64 CC.
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/// This differs from changeFPCCToAArch64CC in that it returns cond codes that
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/// should be AND'ed instead of OR'ed.
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static void changeFPCCToANDAArch64CC(ISD::CondCode CC,
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AArch64CC::CondCode &CondCode,
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AArch64CC::CondCode &CondCode2) {
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CondCode2 = AArch64CC::AL;
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switch (CC) {
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default:
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changeFPCCToAArch64CC(CC, CondCode, CondCode2);
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assert(CondCode2 == AArch64CC::AL);
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break;
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case ISD::SETONE:
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// (a one b)
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// == ((a olt b) || (a ogt b))
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// == ((a ord b) && (a une b))
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CondCode = AArch64CC::VC;
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CondCode2 = AArch64CC::NE;
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break;
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case ISD::SETUEQ:
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// (a ueq b)
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// == ((a uno b) || (a oeq b))
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// == ((a ule b) && (a uge b))
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CondCode = AArch64CC::PL;
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CondCode2 = AArch64CC::LE;
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break;
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}
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}
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/// changeVectorFPCCToAArch64CC - Convert a DAG fp condition code to an AArch64
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/// CC usable with the vector instructions. Fewer operations are available
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/// without a real NZCV register, so we have to use less efficient combinations
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@ -1344,24 +1373,23 @@ static SDValue emitConjunctionDisjunctionTree(SelectionDAG &DAG, SDValue Val,
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} else {
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assert(LHS.getValueType().isFloatingPoint());
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AArch64CC::CondCode ExtraCC;
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changeFPCCToAArch64CC(CC, OutCC, ExtraCC);
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// Surpisingly some floating point conditions can't be tested with a
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// single condition code. Construct an additional comparison in this case.
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// See comment below on how we deal with OR conditions.
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changeFPCCToANDAArch64CC(CC, OutCC, ExtraCC);
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// Some floating point conditions can't be tested with a single condition
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// code. Construct an additional comparison in this case.
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if (ExtraCC != AArch64CC::AL) {
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SDValue ExtraCmp;
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if (!CCOp.getNode())
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ExtraCmp = emitComparison(LHS, RHS, CC, DL, DAG);
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else {
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SDValue ConditionOp = DAG.getConstant(Predicate, DL, MVT_CC);
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// Note that we want the inverse of ExtraCC, so NZCV is not inversed.
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(ExtraCC);
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AArch64CC::CondCode InvExtraCC =
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AArch64CC::getInvertedCondCode(ExtraCC);
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unsigned NZCV = AArch64CC::getNZCVToSatisfyCondCode(InvExtraCC);
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ExtraCmp = emitConditionalComparison(LHS, RHS, CC, CCOp, ConditionOp,
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NZCV, DL, DAG);
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}
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CCOp = ExtraCmp;
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Predicate = AArch64CC::getInvertedCondCode(ExtraCC);
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OutCC = AArch64CC::getInvertedCondCode(OutCC);
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Predicate = ExtraCC;
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}
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}
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@ -317,24 +317,6 @@ define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
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ret i64 %sel
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}
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; CHECK-LABEL: select_complicated
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define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) {
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; CHECK: ldr [[REG:d[0-9]+]],
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; CHECK: fcmp d0, d2
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; CHECK-NEXT: fmov d2, #13.00000000
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; CHECK-NEXT: fccmp d1, d2, #4, ne
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; CHECK-NEXT: fccmp d0, d1, #1, ne
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; CHECK-NEXT: fccmp d0, d1, #4, vc
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; CEHCK-NEXT: csel w0, w0, w1, eq
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%1 = fcmp one double %v1, %v2
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%2 = fcmp oeq double %v2, 13.0
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%3 = fcmp oeq double %v1, 42.0
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%or0 = or i1 %2, %3
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%or1 = or i1 %1, %or0
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%sel = select i1 %or1, i16 %a, i16 %b
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ret i16 %sel
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}
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; CHECK-LABEL: gccbug
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define i64 @gccbug(i64 %x0, i64 %x1) {
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; CHECK: cmp x0, #2
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@ -443,3 +425,163 @@ define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
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store volatile i32 %ext, i32* @g
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ret i64 %sel
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}
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; Test the IR CCs that expand to two cond codes.
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; CHECK-LABEL: _select_and_olt_one:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #4, mi
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; CHECK-NEXT: fccmp d2, d3, #1, ne
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; CHECK-NEXT: csel w0, w0, w1, vc
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; CHECK-NEXT: ret
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define i32 @select_and_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp one double %v2, %v3
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%cr = and i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_and_one_olt:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d0, d1, #1, ne
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; CHECK-NEXT: fccmp d2, d3, #0, vc
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; CHECK-NEXT: csel w0, w0, w1, mi
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; CHECK-NEXT: ret
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define i32 @select_and_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp one double %v0, %v1
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%c1 = fcmp olt double %v2, %v3
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%cr = and i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_and_olt_ueq:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #0, mi
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; CHECK-NEXT: fccmp d2, d3, #8, le
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; CHECK-NEXT: csel w0, w0, w1, pl
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; CHECK-NEXT: ret
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define i32 @select_and_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp ueq double %v2, %v3
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%cr = and i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_and_ueq_olt:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d0, d1, #8, le
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; CHECK-NEXT: fccmp d2, d3, #0, pl
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; CHECK-NEXT: csel w0, w0, w1, mi
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; CHECK-NEXT: ret
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define i32 @select_and_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp ueq double %v0, %v1
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%c1 = fcmp olt double %v2, %v3
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%cr = and i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_olt_one:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #0, pl
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; CHECK-NEXT: fccmp d2, d3, #8, le
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; CHECK-NEXT: csel w0, w0, w1, mi
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; CHECK-NEXT: ret
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define i32 @select_or_olt_one(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp one double %v2, %v3
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%cr = or i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_one_olt:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d0, d1, #1, ne
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; CHECK-NEXT: fccmp d2, d3, #8, vs
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; CHECK-NEXT: csel w0, w0, w1, mi
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; CHECK-NEXT: ret
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define i32 @select_or_one_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp one double %v0, %v1
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%c1 = fcmp olt double %v2, %v3
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%cr = or i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_olt_ueq:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #4, pl
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; CHECK-NEXT: fccmp d2, d3, #1, ne
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; CHECK-NEXT: csel w0, w0, w1, vs
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; CHECK-NEXT: ret
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define i32 @select_or_olt_ueq(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp ueq double %v2, %v3
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%cr = or i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_ueq_olt:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d0, d1, #8, le
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; CHECK-NEXT: fccmp d2, d3, #8, mi
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; CHECK-NEXT: csel w0, w0, w1, mi
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; CHECK-NEXT: ret
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define i32 @select_or_ueq_olt(double %v0, double %v1, double %v2, double %v3, i32 %a, i32 %b) #0 {
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%c0 = fcmp ueq double %v0, %v1
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%c1 = fcmp olt double %v2, %v3
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%cr = or i1 %c1, %c0
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_olt_ogt_ueq:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #0, pl
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; CHECK-NEXT: fccmp d4, d5, #4, le
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; CHECK-NEXT: fccmp d4, d5, #1, ne
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; CHECK-NEXT: csel w0, w0, w1, vs
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; CHECK-NEXT: ret
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define i32 @select_or_olt_ogt_ueq(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp ogt double %v2, %v3
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%c2 = fcmp ueq double %v4, %v5
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%c3 = or i1 %c1, %c0
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%cr = or i1 %c2, %c3
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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; CHECK-LABEL: _select_or_olt_ueq_ogt:
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; CHECK-LABEL: ; BB#0:
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: fccmp d2, d3, #4, pl
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; CHECK-NEXT: fccmp d2, d3, #1, ne
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; CHECK-NEXT: fccmp d4, d5, #0, vc
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; CHECK-NEXT: csel w0, w0, w1, gt
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; CHECK-NEXT: ret
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define i32 @select_or_olt_ueq_ogt(double %v0, double %v1, double %v2, double %v3, double %v4, double %v5, i32 %a, i32 %b) #0 {
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%c0 = fcmp olt double %v0, %v1
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%c1 = fcmp ueq double %v2, %v3
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%c2 = fcmp ogt double %v4, %v5
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%c3 = or i1 %c1, %c0
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%cr = or i1 %c2, %c3
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%sel = select i1 %cr, i32 %a, i32 %b
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ret i32 %sel
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}
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attributes #0 = { nounwind }
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