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[X86] Add ImmArg markings to intrinsics. 

Remove test cases that checked for not crashing when immediate operands were passed not an immediate. These are now considered ill-formed in IR.

This was done by manually scanning the intrinsic file for llvm_i32_ty and llvm_i8_ty which are the predominant types we use for immediates. Most of them are on vector intrinsics. I might have missed some other intrinsics.

Differential Revision: https://reviews.llvm.org/D58302

llvm-svn: 355993
This commit is contained in:
Craig Topper 2019-03-12 23:48:07 +00:00
parent e62366bf1e
commit 9bae5ba076
3 changed files with 422 additions and 381 deletions
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776
llvm/include/llvm/IR/IntrinsicsX86.td
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File diff suppressed because it is too large Load Diff

15
llvm/test/CodeGen/X86/pr33772.ll
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@ -1,15 +0,0 @@
; RUN: not llc < %s -mcpu=skylake-avx512 2>&1 | FileCheck %s
target triple = "x86_64-unknown-linux-gnu"
; make sure we don't crash if scale for gather isn't constant.
; CHECK: LLVM ERROR: Cannot select: intrinsic %llvm.x86.avx512.gather.dpi.512
declare <16 x i32> @llvm.x86.avx512.gather.dpi.512(<16 x i32>, i8*, <16 x i32>, i16, i32)
define internal <16 x i32> @__gather_base_offsets32_i32(i8* readonly %ptr, i32 %offset_scale, <16 x i32> %offsets, <16 x i8> %vecmask) {
%mask_vec_i1.i.i = icmp ne <16 x i8> %vecmask, zeroinitializer
%mask_i16.i = bitcast <16 x i1> %mask_vec_i1.i.i to i16
%res = tail call <16 x i32> @llvm.x86.avx512.gather.dpi.512(<16 x i32> undef, i8* %ptr, <16 x i32> %offsets, i16 %mask_i16.i, i32 %offset_scale)
ret <16 x i32> %res
}

12
llvm/test/Transforms/InstCombine/X86/x86-insertps.ll
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@ -3,18 +3,6 @@
declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i8) nounwind readnone
; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
define <4 x float> @insertps_non_const_imm(<4 x float> %v1, <4 x float> %v2, i8 %c) {
; CHECK-LABEL: @insertps_non_const_imm(
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
; CHECK-NEXT: ret <4 x float> [[RES]]
;
%res = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %v1, <4 x float> %v2, i8 %c)
ret <4 x float> %res
}
; If all zero mask bits are set, return a zero regardless of the other control bits.
define <4 x float> @insertps_0x0f(<4 x float> %v1, <4 x float> %v2) {