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Return const refefrences to enable default construction 

llvm-svn: 4713
This commit is contained in:
Chris Lattner 2002-11-17 21:02:42 +00:00
parent 6fd0ef303d
commit 9fbccc672d
1 changed files with 8 additions and 7 deletions
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15
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
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@ -29,14 +29,15 @@ struct MachineInstrBuilder {
/// addReg - Add a new virtual register operand... /// addReg - Add a new virtual register operand...
/// ///
MachineInstrBuilder &addReg(int RegNo, bool isDef = false) { const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const {
MI->addRegOperand(RegNo, isDef); MI->addRegOperand(RegNo, isDef);
return *this; return *this;
} }
/// addReg - Add an LLVM value that is to be used as a register... /// addReg - Add an LLVM value that is to be used as a register...
/// ///
MachineInstrBuilder &addReg(Value *V, bool isDef = false, bool isDNU = false){ const MachineInstrBuilder &addReg(Value *V, bool isDef = false,
bool isDNU = false) const {
MI->addRegOperand(V, isDef, isDNU); MI->addRegOperand(V, isDef, isDNU);
return *this; return *this;
} }
@ -45,7 +46,7 @@ struct MachineInstrBuilder {
/// register. Useful for instructions that always clobber certain hard regs. /// register. Useful for instructions that always clobber certain hard regs.
/// (Same as addReg(RegNo, true) but shorter and more obvious). /// (Same as addReg(RegNo, true) but shorter and more obvious).
/// ///
MachineInstrBuilder &addClobber(int RegNo) { const MachineInstrBuilder &addClobber(int RegNo) const {
MI->addRegOperand(RegNo, true); MI->addRegOperand(RegNo, true);
return *this; return *this;
} }
@ -53,28 +54,28 @@ struct MachineInstrBuilder {
/// addPCDisp - Add an LLVM value to be treated as a PC relative /// addPCDisp - Add an LLVM value to be treated as a PC relative
/// displacement... /// displacement...
/// ///
MachineInstrBuilder &addPCDisp(Value *V) { const MachineInstrBuilder &addPCDisp(Value *V) const {
MI->addPCDispOperand(V); MI->addPCDispOperand(V);
return *this; return *this;
} }
/// addMReg - Add a machine register operand... /// addMReg - Add a machine register operand...
/// ///
MachineInstrBuilder &addMReg(int Reg, bool isDef=false) { const MachineInstrBuilder &addMReg(int Reg, bool isDef = false) const {
MI->addMachineRegOperand(Reg, isDef); MI->addMachineRegOperand(Reg, isDef);
return *this; return *this;
} }
/// addSImm - Add a new sign extended immediate operand... /// addSImm - Add a new sign extended immediate operand...
/// ///
MachineInstrBuilder &addSImm(int64_t val) { const MachineInstrBuilder &addSImm(int64_t val) const {
MI->addSignExtImmOperand(val); MI->addSignExtImmOperand(val);
return *this; return *this;
} }
/// addZImm - Add a new zero extended immediate operand... /// addZImm - Add a new zero extended immediate operand...
/// ///
MachineInstrBuilder &addZImm(int64_t Val) { const MachineInstrBuilder &addZImm(int64_t Val) const {
MI->addZeroExtImmOperand(Val); MI->addZeroExtImmOperand(Val);
return *this; return *this;
} }