[AVX512] Use alignedstore256 in a pattern that's emitting a 256-bit movaps from an extract subvector operation.
llvm-svn: 311263
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@ -3721,8 +3721,8 @@ let Predicates = [HasVLX] in {
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def : Pat<(alignedstore256 (v4f64 (extract_subvector
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def : Pat<(alignedstore256 (v4f64 (extract_subvector
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(v8f64 VR512:$src), (iPTR 0))), addr:$dst),
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(v8f64 VR512:$src), (iPTR 0))), addr:$dst),
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(VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
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(VMOVAPDZ256mr addr:$dst, (v4f64 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
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def : Pat<(alignedstore (v8f32 (extract_subvector
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def : Pat<(alignedstore256 (v8f32 (extract_subvector
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(v16f32 VR512:$src), (iPTR 0))), addr:$dst),
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(v16f32 VR512:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
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(VMOVAPSZ256mr addr:$dst, (v8f32 (EXTRACT_SUBREG VR512:$src,sub_ymm)))>;
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def : Pat<(alignedstore256 (v4i64 (extract_subvector
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def : Pat<(alignedstore256 (v4i64 (extract_subvector
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(v8i64 VR512:$src), (iPTR 0))), addr:$dst),
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(v8i64 VR512:$src), (iPTR 0))), addr:$dst),
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@ -493,7 +493,7 @@ entry:
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define void @extract_subvector512_v8f32_store_lo_align_16(float* nocapture %addr, <16 x float> %a) nounwind uwtable ssp {
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define void @extract_subvector512_v8f32_store_lo_align_16(float* nocapture %addr, <16 x float> %a) nounwind uwtable ssp {
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; SKX-LABEL: extract_subvector512_v8f32_store_lo_align_16:
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; SKX-LABEL: extract_subvector512_v8f32_store_lo_align_16:
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; SKX: ## BB#0: ## %entry
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; SKX: ## BB#0: ## %entry
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; SKX-NEXT: vmovaps %ymm0, (%rdi)
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; SKX-NEXT: vmovups %ymm0, (%rdi)
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: vzeroupper
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; SKX-NEXT: retq
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; SKX-NEXT: retq
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entry:
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entry:
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