OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

[PhaseOrdering] add test for vector trunc; NFC 

See discussion in D76983.
This commit is contained in:
Sanjay Patel 2020-04-02 08:12:24 -04:00
parent ecb048c7ac
commit a19b27b90e
1 changed files with 24 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
llvm/test/Transforms/PhaseOrdering/vector-trunc.ll Normal file
View File

@ -0,0 +1,24 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -O2 -S -data-layout="e" < %s | FileCheck %s --check-prefixes=ANY,OLDPM
; RUN: opt -passes='default<O2>' -S -data-layout="e" < %s | FileCheck %s --check-prefixes=ANY,NEWPM
define <4 x i16> @truncate(<4 x i32> %x) {
; ANY-LABEL: @truncate(
; ANY-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[X:%.*]] to <8 x i16>
; ANY-NEXT: [[V3:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
; ANY-NEXT: ret <4 x i16> [[V3]]
;
%x0 = extractelement <4 x i32> %x, i32 0
%t0 = trunc i32 %x0 to i16
%v0 = insertelement <4 x i16> undef, i16 %t0, i32 0
%x1 = extractelement <4 x i32> %x, i32 1
%t1 = trunc i32 %x1 to i16
%v1 = insertelement <4 x i16> %v0, i16 %t1, i32 1
%x2 = extractelement <4 x i32> %x, i32 2
%t2 = trunc i32 %x2 to i16
%v2 = insertelement <4 x i16> %v1, i16 %t2, i32 2
%x3 = extractelement <4 x i32> %x, i32 3
%t3 = trunc i32 %x3 to i16
%v3 = insertelement <4 x i16> %v2, i16 %t3, i32 3
ret <4 x i16> %v3
}