[AArch64][SVE] Implement AArch64ISD::SETCC_PRED
This unifies SETCC operations along the lines of other operations. Differential Revision: https://reviews.llvm.org/D79975
This commit is contained in:
Eli Friedman
parent
015e297a37
commit
a1ce88b4e3
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@ -886,6 +886,8 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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if (VT.getScalarType() == MVT::i1)
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setOperationAction(ISD::SETCC, VT, Custom);
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}
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}
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom);
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@ -1294,6 +1296,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case AArch64ISD::SHL_PRED: return "AArch64ISD::SHL_PRED";
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case AArch64ISD::SRL_PRED: return "AArch64ISD::SRL_PRED";
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case AArch64ISD::SRA_PRED: return "AArch64ISD::SRA_PRED";
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case AArch64ISD::SETCC_PRED: return "AArch64ISD::SETCC_PRED";
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case AArch64ISD::ADC: return "AArch64ISD::ADC";
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case AArch64ISD::SBC: return "AArch64ISD::SBC";
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case AArch64ISD::ADDS: return "AArch64ISD::ADDS";
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@ -7719,7 +7722,9 @@ SDValue AArch64TargetLowering::LowerToPredicatedOp(SDValue Op,
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VT.getVectorNumElements(), true);
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SDValue Mask = getPTrue(DAG, DL, PredTy, AArch64SVEPredPattern::all);
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return DAG.getNode(NewOp, DL, VT, Mask, Op.getOperand(0), Op.getOperand(1));
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SmallVector<SDValue, 4> Operands = {Mask};
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Operands.append(Op->op_begin(), Op->op_end());
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return DAG.getNode(NewOp, DL, VT, Operands);
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}
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static bool resolveBuildVector(BuildVectorSDNode *BVN, APInt &CnstBits,
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@ -8788,6 +8793,12 @@ static SDValue EmitVectorComparison(SDValue LHS, SDValue RHS,
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SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
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SelectionDAG &DAG) const {
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if (Op.getValueType().isScalableVector()) {
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if (Op.getOperand(0).getValueType().isFloatingPoint())
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return Op;
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return LowerToPredicatedOp(Op, DAG, AArch64ISD::SETCC_PRED);
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}
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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@ -11291,8 +11302,7 @@ static SDValue LowerSVEIntrinsicEXT(SDNode *N, SelectionDAG &DAG) {
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return DAG.getNode(ISD::BITCAST, dl, VT, EXT);
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}
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static SDValue tryConvertSVEWideCompare(SDNode *N, unsigned ReplacementIID,
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bool Invert,
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static SDValue tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC,
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TargetLowering::DAGCombinerInfo &DCI,
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SelectionDAG &DAG) {
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if (DCI.isBeforeLegalize())
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@ -11346,17 +11356,8 @@ static SDValue tryConvertSVEWideCompare(SDNode *N, unsigned ReplacementIID,
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}
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SDValue Splat = DAG.getNode(ISD::SPLAT_VECTOR, DL, CmpVT, Imm);
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SDValue ID = DAG.getTargetConstant(ReplacementIID, DL, MVT::i64);
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SDValue Op0, Op1;
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if (Invert) {
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Op0 = Splat;
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Op1 = N->getOperand(2);
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} else {
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Op0 = N->getOperand(2);
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Op1 = Splat;
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}
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
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ID, Pred, Op0, Op1);
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return DAG.getNode(AArch64ISD::SETCC_PRED, DL, VT, Pred, N->getOperand(2),
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Splat, DAG.getCondCode(CC));
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}
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return SDValue();
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@ -11530,6 +11531,42 @@ static SDValue performIntrinsicCombine(SDNode *N,
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case Intrinsic::aarch64_sve_asr:
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return DAG.getNode(AArch64ISD::SRA_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3));
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case Intrinsic::aarch64_sve_cmphs:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETUGE));
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break;
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case Intrinsic::aarch64_sve_cmphi:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETUGT));
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break;
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case Intrinsic::aarch64_sve_cmpge:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETGE));
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break;
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case Intrinsic::aarch64_sve_cmpgt:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETGT));
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break;
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case Intrinsic::aarch64_sve_cmpeq:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETEQ));
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break;
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case Intrinsic::aarch64_sve_cmpne:
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if (!N->getOperand(2).getValueType().isFloatingPoint())
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return DAG.getNode(AArch64ISD::SETCC_PRED, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3),
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DAG.getCondCode(ISD::SETNE));
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break;
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case Intrinsic::aarch64_sve_fadda:
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return combineSVEReductionOrderedFP(N, AArch64ISD::FADDA_PRED, DAG);
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case Intrinsic::aarch64_sve_faddv:
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@ -11546,35 +11583,25 @@ static SDValue performIntrinsicCombine(SDNode *N,
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return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0),
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N->getOperand(1), N->getOperand(2), N->getOperand(3));
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case Intrinsic::aarch64_sve_cmpeq_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpeq,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETEQ, DCI, DAG);
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case Intrinsic::aarch64_sve_cmpne_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpne,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETNE, DCI, DAG);
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case Intrinsic::aarch64_sve_cmpge_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpge,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETGE, DCI, DAG);
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case Intrinsic::aarch64_sve_cmpgt_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpgt,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETGT, DCI, DAG);
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case Intrinsic::aarch64_sve_cmplt_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpgt,
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true, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETLT, DCI, DAG);
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case Intrinsic::aarch64_sve_cmple_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmpge,
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true, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETLE, DCI, DAG);
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case Intrinsic::aarch64_sve_cmphs_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmphs,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETUGE, DCI, DAG);
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case Intrinsic::aarch64_sve_cmphi_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmphi,
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false, DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETUGT, DCI, DAG);
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case Intrinsic::aarch64_sve_cmplo_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmphi, true,
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DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETULT, DCI, DAG);
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case Intrinsic::aarch64_sve_cmpls_wide:
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return tryConvertSVEWideCompare(N, Intrinsic::aarch64_sve_cmphs, true,
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DCI, DAG);
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return tryConvertSVEWideCompare(N, ISD::SETULE, DCI, DAG);
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case Intrinsic::aarch64_sve_ptest_any:
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return getPTest(DAG, N->getValueType(0), N->getOperand(1), N->getOperand(2),
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AArch64CC::ANY_ACTIVE);
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@ -62,6 +62,7 @@ enum NodeType : unsigned {
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SHL_PRED,
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SRL_PRED,
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SRA_PRED,
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SETCC_PRED,
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// Arithmetic instructions which write flags.
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ADDS,
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@ -1005,12 +1005,12 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1", AArch64trn1>;
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defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2", AArch64trn2>;
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defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", int_aarch64_sve_cmphs, SETUGE>;
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defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", int_aarch64_sve_cmphi, SETUGT>;
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defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge", int_aarch64_sve_cmpge, SETGE>;
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defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt", int_aarch64_sve_cmpgt, SETGT>;
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defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq", int_aarch64_sve_cmpeq, SETEQ>;
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defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne", int_aarch64_sve_cmpne, SETNE>;
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defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>;
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defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>;
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defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge", SETGE, SETLE>;
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defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt", SETGT, SETLT>;
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defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq", SETEQ, SETEQ>;
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defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne", SETNE, SETNE>;
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defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq", int_aarch64_sve_cmpeq_wide>;
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defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne", int_aarch64_sve_cmpne_wide>;
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@ -1023,16 +1023,16 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio
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defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo", int_aarch64_sve_cmplo_wide>;
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defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls", int_aarch64_sve_cmpls_wide>;
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defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge", SETGE, int_aarch64_sve_cmpge>;
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defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt", SETGT, int_aarch64_sve_cmpgt>;
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defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, null_frag, int_aarch64_sve_cmpgt>;
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defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple", SETLE, null_frag, int_aarch64_sve_cmpge>;
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defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq", SETEQ, int_aarch64_sve_cmpeq>;
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defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne", SETNE, int_aarch64_sve_cmpne>;
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defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs", SETUGE, int_aarch64_sve_cmphs>;
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defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi", SETUGT, int_aarch64_sve_cmphi>;
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defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo", SETULT, null_frag, int_aarch64_sve_cmphi>;
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defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls", SETULE, null_frag, int_aarch64_sve_cmphs>;
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defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge", SETGE, SETLE>;
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defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt", SETGT, SETLT>;
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defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, SETGT>;
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defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple", SETLE, SETGE>;
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defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq", SETEQ, SETEQ>;
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defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne", SETNE, SETEQ>;
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defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs", SETUGE, SETULE>;
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defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi", SETUGT, SETULT>;
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defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo", SETULT, SETUGT>;
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defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls", SETULE, SETUGE>;
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defm FCMGE_PPzZZ : sve_fp_3op_p_pd_cc<0b000, "fcmge", int_aarch64_sve_fcmpge, setoge>;
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defm FCMGT_PPzZZ : sve_fp_3op_p_pd_cc<0b001, "fcmgt", int_aarch64_sve_fcmpgt, setogt>;
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@ -10,6 +10,14 @@
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//
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//===----------------------------------------------------------------------===//
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def SDT_AArch64Setcc : SDTypeProfile<1, 4, [
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SDTCisVec<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisVec<3>,
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SDTCVecEltisVT<0, i1>, SDTCVecEltisVT<1, i1>, SDTCisSameAs<2, 3>,
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SDTCisVT<4, OtherVT>
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]>;
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def AArch64setcc_pred : SDNode<"AArch64ISD::SETCC_PRED", SDT_AArch64Setcc>;
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def SVEPatternOperand : AsmOperandClass {
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let Name = "SVEPattern";
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let ParserMethod = "tryParseSVEPattern";
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@ -4147,17 +4155,24 @@ class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
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let Defs = [NZCV];
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}
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multiclass sve_int_cmp_0<bits<3> opc, string asm, SDPatternOperator op,
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CondCode cc> {
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multiclass SVE_SETCC_Pat<CondCode cc, CondCode invcc, ValueType predvt,
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ValueType intvt, sve_int_cmp cmp> {
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def : Pat<(predvt (AArch64setcc_pred predvt:$Op1, intvt:$Op2, intvt:$Op3, cc)),
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(cmp $Op1, $Op2, $Op3)>;
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def : Pat<(predvt (AArch64setcc_pred predvt:$Op1, intvt:$Op2, intvt:$Op3, invcc)),
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(cmp $Op1, $Op3, $Op2)>;
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}
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multiclass sve_int_cmp_0<bits<3> opc, string asm, CondCode cc, CondCode invcc> {
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def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
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def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
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def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
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def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
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def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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defm : SVE_SETCC_Pat<cc, invcc, nxv16i1, nxv16i8, !cast<Instruction>(NAME # _B)>;
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defm : SVE_SETCC_Pat<cc, invcc, nxv8i1, nxv8i16, !cast<Instruction>(NAME # _H)>;
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defm : SVE_SETCC_Pat<cc, invcc, nxv4i1, nxv4i32, !cast<Instruction>(NAME # _S)>;
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defm : SVE_SETCC_Pat<cc, invcc, nxv2i1, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_cmp_0_wide<bits<3> opc, string asm, SDPatternOperator op> {
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@ -4212,67 +4227,35 @@ class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
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let ElementSize = pprty.ElementSize;
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}
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multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc,
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SDPatternOperator op = null_frag,
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SDPatternOperator inv_op = null_frag> {
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multiclass SVE_SETCC_Imm_Pat<CondCode cc, CondCode commuted_cc,
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ValueType predvt, ValueType intvt,
|
||||
Operand immtype, Instruction cmp> {
|
||||
def : Pat<(predvt (AArch64setcc_pred (predvt PPR_3b:$Pg),
|
||||
(intvt ZPR:$Zs1),
|
||||
(intvt (AArch64dup (immtype:$imm))),
|
||||
cc)),
|
||||
(cmp $Pg, $Zs1, immtype:$imm)>;
|
||||
def : Pat<(predvt (AArch64setcc_pred (predvt PPR_3b:$Pg),
|
||||
(intvt (AArch64dup (immtype:$imm))),
|
||||
(intvt ZPR:$Zs1),
|
||||
commuted_cc)),
|
||||
(cmp $Pg, $Zs1, immtype:$imm)>;
|
||||
}
|
||||
|
||||
multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc, CondCode commuted_cc> {
|
||||
def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
|
||||
def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
|
||||
def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
|
||||
def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
|
||||
|
||||
// IR version
|
||||
def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
|
||||
(nxv16i8 (AArch64dup (simm5_32b:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
|
||||
(nxv8i16 (AArch64dup (simm5_32b:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
|
||||
(nxv4i32 (AArch64dup (simm5_32b:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
|
||||
(nxv2i64 (AArch64dup (simm5_64b:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, simm5_64b:$imm)>;
|
||||
|
||||
// Intrinsic version
|
||||
def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
|
||||
(nxv16i8 ZPR:$Zs1),
|
||||
(nxv16i8 (AArch64dup (simm5_32b:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
|
||||
(nxv8i16 ZPR:$Zs1),
|
||||
(nxv8i16 (AArch64dup (simm5_32b:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
|
||||
(nxv4i32 ZPR:$Zs1),
|
||||
(nxv4i32 (AArch64dup (simm5_32b:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
|
||||
(nxv2i64 ZPR:$Zs1),
|
||||
(nxv2i64 (AArch64dup (simm5_64b:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
|
||||
|
||||
// Inverted intrinsic version
|
||||
def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
|
||||
(nxv16i8 (AArch64dup (simm5_32b:$imm))),
|
||||
(nxv16i8 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
|
||||
(nxv8i16 (AArch64dup (simm5_32b:$imm))),
|
||||
(nxv8i16 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
|
||||
(nxv4i32 (AArch64dup (simm5_32b:$imm))),
|
||||
(nxv4i32 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
|
||||
def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
|
||||
(nxv2i64 (AArch64dup (simm5_64b:$imm))),
|
||||
(nxv2i64 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv16i1, nxv16i8, simm5_32b,
|
||||
!cast<Instruction>(NAME # _B)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv8i1, nxv8i16, simm5_32b,
|
||||
!cast<Instruction>(NAME # _H)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv4i1, nxv4i32, simm5_32b,
|
||||
!cast<Instruction>(NAME # _S)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv2i1, nxv2i64, simm5_64b,
|
||||
!cast<Instruction>(NAME # _D)>;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -4304,66 +4287,20 @@ class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
|
|||
}
|
||||
|
||||
multiclass sve_int_ucmp_vi<bits<2> opc, string asm, CondCode cc,
|
||||
SDPatternOperator op = null_frag,
|
||||
SDPatternOperator inv_op = null_frag> {
|
||||
CondCode commuted_cc> {
|
||||
def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
|
||||
def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
|
||||
def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
|
||||
def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127_64b>;
|
||||
|
||||
// IR version
|
||||
def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
|
||||
(nxv16i8 (AArch64dup (imm0_127:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
|
||||
(nxv8i16 (AArch64dup (imm0_127:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
|
||||
(nxv4i32 (AArch64dup (imm0_127:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
|
||||
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
|
||||
cc)),
|
||||
(!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, imm0_127_64b:$imm)>;
|
||||
|
||||
// Intrinsic version
|
||||
def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
|
||||
(nxv16i8 ZPR:$Zs1),
|
||||
(nxv16i8 (AArch64dup (imm0_127:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
|
||||
(nxv8i16 ZPR:$Zs1),
|
||||
(nxv8i16 (AArch64dup (imm0_127:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
|
||||
(nxv4i32 ZPR:$Zs1),
|
||||
(nxv4i32 (AArch64dup (imm0_127:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
|
||||
(nxv2i64 ZPR:$Zs1),
|
||||
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))))),
|
||||
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
|
||||
|
||||
// Inverted intrinsic version
|
||||
def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
|
||||
(nxv16i8 (AArch64dup (imm0_127:$imm))),
|
||||
(nxv16i8 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
|
||||
(nxv8i16 (AArch64dup (imm0_127:$imm))),
|
||||
(nxv8i16 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
|
||||
(nxv4i32 (AArch64dup (imm0_127:$imm))),
|
||||
(nxv4i32 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
|
||||
def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
|
||||
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
|
||||
(nxv2i64 ZPR:$Zs1))),
|
||||
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv16i1, nxv16i8, imm0_127,
|
||||
!cast<Instruction>(NAME # _B)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv8i1, nxv8i16, imm0_127,
|
||||
!cast<Instruction>(NAME # _H)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv4i1, nxv4i32, imm0_127,
|
||||
!cast<Instruction>(NAME # _S)>;
|
||||
defm : SVE_SETCC_Imm_Pat<cc, commuted_cc, nxv2i1, nxv2i64, imm0_127_64b,
|
||||
!cast<Instruction>(NAME # _D)>;
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -74,6 +74,42 @@ define <vscale x 4 x i1> @cmpeq_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpeq_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpeq_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp eq <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpeq_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpeq_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp eq <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpeq_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpeq_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp eq <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpeq_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpeq_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp eq <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
;
|
||||
; CMPGE
|
||||
;
|
||||
|
|
@ -148,6 +184,78 @@ define <vscale x 4 x i1> @cmpge_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpge_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sge <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpge_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpge p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sge <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpge_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sge <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpge_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpge p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sge <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpge_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_comm_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpge p0.b, p0/z, z1.b, z0.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sle <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpge_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_comm_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpge p0.h, p0/z, z1.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sle <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpge_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_comm_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpge p0.s, p0/z, z1.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sle <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpge_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpge_ir_comm_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpge p0.d, p0/z, z1.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sle <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
;
|
||||
; CMPGT
|
||||
;
|
||||
|
|
@ -222,6 +330,78 @@ define <vscale x 4 x i1> @cmpgt_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpgt_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpgt p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sgt <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpgt_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpgt p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sgt <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpgt_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpgt p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sgt <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpgt_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpgt p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp sgt <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpgt_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_comm_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpgt p0.b, p0/z, z1.b, z0.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp slt <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpgt_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_comm_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpgt p0.h, p0/z, z1.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp slt <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpgt_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_comm_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpgt p0.s, p0/z, z1.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp slt <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpgt_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpgt_ir_comm_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpgt p0.d, p0/z, z1.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp slt <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
;
|
||||
; CMPHI
|
||||
;
|
||||
|
|
@ -296,6 +476,78 @@ define <vscale x 4 x i1> @cmphi_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmphi_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmphi p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ugt <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmphi_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmphi p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ugt <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmphi_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmphi p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ugt <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmphi_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmphi p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ugt <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmphi_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_comm_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmphi p0.b, p0/z, z1.b, z0.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ult <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmphi_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_comm_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmphi p0.h, p0/z, z1.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ult <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmphi_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_comm_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmphi p0.s, p0/z, z1.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ult <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmphi_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmphi_ir_comm_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmphi p0.d, p0/z, z1.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ult <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
;
|
||||
; CMPHS
|
||||
;
|
||||
|
|
@ -370,6 +622,78 @@ define <vscale x 4 x i1> @cmphs_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmphs_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmphs p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp uge <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmphs_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmphs p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp uge <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmphs_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmphs p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp uge <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmphs_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmphs p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp uge <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmphs_ir_comm_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_comm_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmphs p0.b, p0/z, z1.b, z0.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ule <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmphs_ir_comm_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_comm_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmphs p0.h, p0/z, z1.h, z0.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ule <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmphs_ir_comm_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_comm_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmphs p0.s, p0/z, z1.s, z0.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ule <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmphs_ir_comm_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmphs_ir_comm_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmphs p0.d, p0/z, z1.d, z0.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ule <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
;
|
||||
; CMPLE
|
||||
;
|
||||
|
|
@ -580,6 +904,42 @@ define <vscale x 4 x i1> @cmpne_wide_s(<vscale x 4 x i1> %pg, <vscale x 4 x i32>
|
|||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 16 x i1> @cmpne_ir_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: cmpne_ir_b:
|
||||
; CHECK: ptrue p0.b
|
||||
; CHECK-NEXT: cmpne p0.b, p0/z, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ne <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i1> @cmpne_ir_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: cmpne_ir_h:
|
||||
; CHECK: ptrue p0.h
|
||||
; CHECK-NEXT: cmpne p0.h, p0/z, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ne <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i1> @cmpne_ir_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: cmpne_ir_s:
|
||||
; CHECK: ptrue p0.s
|
||||
; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ne <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i1> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i1> @cmpne_ir_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: cmpne_ir_d:
|
||||
; CHECK: ptrue p0.d
|
||||
; CHECK-NEXT: cmpne p0.d, p0/z, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = icmp ne <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i1> %out
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpeq.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpeq.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
|
|
|
|||
Loading…
Reference in New Issue