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[AArch64] Refine Falkor machine description for pre/post-inc and stores. 

llvm-svn: 300892
This commit is contained in:
Chad Rosier 2017-04-20 21:11:09 +00:00
parent 58bef5d8e8
commit a56bdbe62d
1 changed files with 5 additions and 5 deletions
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llvm/lib/Target/AArch64/AArch64SchedFalkor.td
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@ -79,14 +79,14 @@ def : WriteRes<WriteIM64, [FalkorUnitX]> { let Latency = 5; }
def : WriteRes<WriteBr, [FalkorUnitB]> { let Latency = 1; } def : WriteRes<WriteBr, [FalkorUnitB]> { let Latency = 1; }
def : WriteRes<WriteBrReg, [FalkorUnitB]> { let Latency = 1; } def : WriteRes<WriteBrReg, [FalkorUnitB]> { let Latency = 1; }
def : WriteRes<WriteLD, [FalkorUnitLD]> { let Latency = 3; } def : WriteRes<WriteLD, [FalkorUnitLD]> { let Latency = 3; }
def : WriteRes<WriteST, [FalkorUnitLD, FalkorUnitST, FalkorUnitSD]> def : WriteRes<WriteST, [FalkorUnitST, FalkorUnitSD]>
{ let Latency = 3; let NumMicroOps = 3; } { let Latency = 0; let NumMicroOps = 2; }
def : WriteRes<WriteSTP, [FalkorUnitST, FalkorUnitSD]> def : WriteRes<WriteSTP, [FalkorUnitST, FalkorUnitSD]>
{ let Latency = 0; let NumMicroOps = 2; } { let Latency = 0; let NumMicroOps = 2; }
def : WriteRes<WriteAdr, [FalkorUnitXYZ]> { let Latency = 5; } def : WriteRes<WriteAdr, [FalkorUnitXYZ]> { let Latency = 1; }
def : WriteRes<WriteLDIdx, [FalkorUnitLD]> { let Latency = 5; } def : WriteRes<WriteLDIdx, [FalkorUnitLD]> { let Latency = 5; }
def : WriteRes<WriteSTIdx, [FalkorUnitLD, FalkorUnitST, FalkorUnitSD]> def : WriteRes<WriteSTIdx, [FalkorUnitST, FalkorUnitSD]>
{ let Latency = 4; let NumMicroOps = 3; } { let Latency = 0; let NumMicroOps = 3; }
def : WriteRes<WriteF, [FalkorUnitVXVY, FalkorUnitVXVY]> def : WriteRes<WriteF, [FalkorUnitVXVY, FalkorUnitVXVY]>
{ let Latency = 3; let NumMicroOps = 2; } { let Latency = 3; let NumMicroOps = 2; }
def : WriteRes<WriteFCmp, [FalkorUnitVXVY]> { let Latency = 2; } def : WriteRes<WriteFCmp, [FalkorUnitVXVY]> { let Latency = 2; }