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[RISCV] Improve assembler missing feature warnings 

This adds support for printing improved missing feature error messages
from the assembler, which now indicates which feature caused the parse
to fail.

Differential Revision: https://reviews.llvm.org/D69899
This commit is contained in:
Simon Cook 2019-12-10 16:44:48 +00:00
parent 0be81968a2
commit a6e50e40e6
16 changed files with 174 additions and 133 deletions
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20
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
View File

@ -738,6 +738,7 @@ public:
} // end anonymous namespace. } // end anonymous namespace.
#define GET_REGISTER_MATCHER #define GET_REGISTER_MATCHER
#define GET_SUBTARGET_FEATURE_NAME
#define GET_MATCHER_IMPLEMENTATION #define GET_MATCHER_IMPLEMENTATION
#define GET_MNEMONIC_SPELL_CHECKER #define GET_MNEMONIC_SPELL_CHECKER
#include "RISCVGenAsmMatcher.inc" #include "RISCVGenAsmMatcher.inc"
@ -786,16 +787,29 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
uint64_t &ErrorInfo, uint64_t &ErrorInfo,
bool MatchingInlineAsm) { bool MatchingInlineAsm) {
MCInst Inst; MCInst Inst;
FeatureBitset MissingFeatures;
auto Result = auto Result =
MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm); MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
MatchingInlineAsm);
switch (Result) { switch (Result) {
default: default:
break; break;
case Match_Success: case Match_Success:
return processInstruction(Inst, IDLoc, Operands, Out); return processInstruction(Inst, IDLoc, Operands, Out);
case Match_MissingFeature: case Match_MissingFeature: {
return Error(IDLoc, "instruction use requires an option to be enabled"); assert(MissingFeatures.any() && "Unknown missing features!");
bool FirstFeature = true;
std::string Msg = "instruction requires the following:";
for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) {
if (MissingFeatures[i]) {
Msg += FirstFeature ? " " : ", ";
Msg += getSubtargetFeatureName(i);
FirstFeature = false;
}
}
return Error(IDLoc, Msg);
}
case Match_MnemonicFail: { case Match_MnemonicFail: {
FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
std::string Suggestion = RISCVMnemonicSpellCheck( std::string Suggestion = RISCVMnemonicSpellCheck(

24
llvm/lib/Target/RISCV/RISCV.td
View File

@ -16,45 +16,53 @@ def FeatureStdExtM
: SubtargetFeature<"m", "HasStdExtM", "true", : SubtargetFeature<"m", "HasStdExtM", "true",
"'M' (Integer Multiplication and Division)">; "'M' (Integer Multiplication and Division)">;
def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">, def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
AssemblerPredicate<"FeatureStdExtM">; AssemblerPredicate<"FeatureStdExtM",
"'M' (Integer Multiplication and Division)">;
def FeatureStdExtA def FeatureStdExtA
: SubtargetFeature<"a", "HasStdExtA", "true", : SubtargetFeature<"a", "HasStdExtA", "true",
"'A' (Atomic Instructions)">; "'A' (Atomic Instructions)">;
def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">, def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
AssemblerPredicate<"FeatureStdExtA">; AssemblerPredicate<"FeatureStdExtA",
"'A' (Atomic Instructions)">;
def FeatureStdExtF def FeatureStdExtF
: SubtargetFeature<"f", "HasStdExtF", "true", : SubtargetFeature<"f", "HasStdExtF", "true",
"'F' (Single-Precision Floating-Point)">; "'F' (Single-Precision Floating-Point)">;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">, def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<"FeatureStdExtF">; AssemblerPredicate<"FeatureStdExtF",
"'F' (Single-Precision Floating-Point)">;
def FeatureStdExtD def FeatureStdExtD
: SubtargetFeature<"d", "HasStdExtD", "true", : SubtargetFeature<"d", "HasStdExtD", "true",
"'D' (Double-Precision Floating-Point)", "'D' (Double-Precision Floating-Point)",
[FeatureStdExtF]>; [FeatureStdExtF]>;
def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">, def HasStdExtD : Predicate<"Subtarget->hasStdExtD()">,
AssemblerPredicate<"FeatureStdExtD">; AssemblerPredicate<"FeatureStdExtD",
"'D' (Double-Precision Floating-Point)">;
def FeatureStdExtC def FeatureStdExtC
: SubtargetFeature<"c", "HasStdExtC", "true", : SubtargetFeature<"c", "HasStdExtC", "true",
"'C' (Compressed Instructions)">; "'C' (Compressed Instructions)">;
def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">, def HasStdExtC : Predicate<"Subtarget->hasStdExtC()">,
AssemblerPredicate<"FeatureStdExtC">; AssemblerPredicate<"FeatureStdExtC",
"'C' (Compressed Instructions)">;
def FeatureRVCHints def FeatureRVCHints
: SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true", : SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
"Enable RVC Hint Instructions.">; "Enable RVC Hint Instructions.">;
def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">, def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
AssemblerPredicate<"FeatureRVCHints">; AssemblerPredicate<"FeatureRVCHints",
"RVC Hint Instructions">;
def Feature64Bit def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">, def IsRV64 : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<"Feature64Bit">; AssemblerPredicate<"Feature64Bit",
"RV64I Base Instruction Set">;
def IsRV32 : Predicate<"!Subtarget->is64Bit()">, def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<"!Feature64Bit">; AssemblerPredicate<"!Feature64Bit",
"RV32I Base Instruction Set">;
def RV64 : HwMode<"+64bit">; def RV64 : HwMode<"+64bit">;
def RV32 : HwMode<"-64bit">; def RV32 : HwMode<"-64bit">;

8
llvm/test/MC/RISCV/rv32c-invalid.s
View File

@ -22,15 +22,15 @@ c.lwsp zero, 4(sp) # CHECK: :[[@LINE]]:9: error: invalid operand for instructio
c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction c.jr x0 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
c.jalr zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction c.jalr zero # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
c.addi x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero c.addi x0, x0, 1 # CHECK: :[[@LINE]]:13: error: immediate must be zero
c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled c.li zero, 2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
c.slli zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction c.slli zero, zero, 4 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled c.mv zero, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction c.mv ra, x0 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction c.add ra, ra, x0 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
c.add zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction c.add zero, zero, sp # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
## GPRNoX0X2 ## GPRNoX0X2
c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled c.lui x0, 4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction c.lui x2, 4 # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
## SP ## SP
@ -55,7 +55,7 @@ c.andi a0, %lo(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer
c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31] c.andi a0, %hi(foo) # CHECK: :[[@LINE]]:12: error: immediate must be an integer in the range [-32, 31]
## simm6nonzero ## simm6nonzero
c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled c.addi t0, 0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RVC Hint Instructions
c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] c.addi t0, -33 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] c.addi t0, 32 # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]
c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31] c.addi t0, foo # CHECK: :[[@LINE]]:12: error: immediate must be non-zero in the range [-32, 31]

11
llvm/test/MC/RISCV/rv32c-only-valid.s
View File

@ -9,11 +9,14 @@
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
# RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: not llvm-mc -triple riscv64 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-RV32 %s
# RUN: not llvm-mc -triple riscv64 \
# FIXME: error message for c.jal with rv64c is misleading # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-RV32-AND-EXT %s
# CHECK-ASM-AND-OBJ: c.jal 2046 # CHECK-ASM-AND-OBJ: c.jal 2046
# CHECK-ASM: encoding: [0xfd,0x2f] # CHECK-ASM: encoding: [0xfd,0x2f]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
# CHECK-NO-RV32-AND-EXT: error: instruction requires the following: 'C' (Compressed Instructions), RV32I Base Instruction Set
c.jal 2046 c.jal 2046

16
llvm/test/MC/RISCV/rv32dc-valid.s
View File

@ -6,24 +6,28 @@
# #
# RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: not llvm-mc -triple riscv32 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
# RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)
# CHECK-ASM: encoding: [0x7e,0x34] # CHECK-ASM: encoding: [0x7e,0x34]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fldsp fs0, 504(sp) c.fldsp fs0, 504(sp)
# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp)
# CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-ASM: encoding: [0xc6,0xbf]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fsdsp fa7, 504(sp) c.fsdsp fa7, 504(sp)
# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5)
# CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-ASM: encoding: [0xf4,0x3f]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fld fa3, 248(a5) c.fld fa3, 248(a5)
# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1)
# CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-ASM: encoding: [0xf0,0xbd]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fsd fa2, 248(a1) c.fsd fa2, 248(a1)

2
llvm/test/MC/RISCV/rv32f-invalid.s
View File

@ -29,6 +29,6 @@ fmsub.s f14, f15, f16, f17, 0 # CHECK: :[[@LINE]]:29: error: operand must be a v
fnmsub.s f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic fnmsub.s f18, f19, f20, f21, 0b111 # CHECK: :[[@LINE]]:30: error: operand must be a valid floating point rounding mode mnemonic
# Using 'D' instructions for an 'F'-only target # Using 'D' instructions for an 'F'-only target
fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled fadd.d ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# Using RV64F instructions for RV32 is tested in rv64f-valid.s # Using RV64F instructions for RV32 is tested in rv64f-valid.s

22
llvm/test/MC/RISCV/rv32fc-valid.s
View File

@ -6,30 +6,38 @@
# #
# RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: not llvm-mc -triple riscv32 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-F %s
# RUN: not llvm-mc -triple riscv32 \ # RUN: not llvm-mc -triple riscv32 \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-FC %s
# RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \ # RUN: not llvm-mc -triple riscv64 -mattr=+c,+f \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-RV32 %s
# FIXME: error messages for rv64fc are misleading # FIXME: error messages for rv64fc are misleading
# CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp) # CHECK-ASM-AND-OBJ: c.flwsp fs0, 252(sp)
# CHECK-ASM: encoding: [0x7e,0x74] # CHECK-ASM: encoding: [0x7e,0x74]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point)
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
c.flwsp fs0, 252(sp) c.flwsp fs0, 252(sp)
# CHECK-ASM-AND-OBJ: c.fswsp fa7, 252(sp) # CHECK-ASM-AND-OBJ: c.fswsp fa7, 252(sp)
# CHECK-ASM: encoding: [0xc6,0xff] # CHECK-ASM: encoding: [0xc6,0xff]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point)
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
c.fswsp fa7, 252(sp) c.fswsp fa7, 252(sp)
# CHECK-ASM-AND-OBJ: c.flw fa3, 124(a5) # CHECK-ASM-AND-OBJ: c.flw fa3, 124(a5)
# CHECK-ASM: encoding: [0xf4,0x7f] # CHECK-ASM: encoding: [0xf4,0x7f]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point)
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
c.flw fa3, 124(a5) c.flw fa3, 124(a5)
# CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1) # CHECK-ASM-AND-OBJ: c.fsw fa2, 124(a1)
# CHECK-ASM: encoding: [0xf0,0xfd] # CHECK-ASM: encoding: [0xf0,0xfd]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-F: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# CHECK-NO-EXT-FC: error: instruction requires the following: 'C' (Compressed Instructions), 'F' (Single-Precision Floating-Point)
# CHECK-NO-RV32: error: instruction requires the following: RV32I Base Instruction Set
c.fsw fa2, 124(a1) c.fsw fa2, 124(a1)

4
llvm/test/MC/RISCV/rv32i-aliases-invalid.s
View File

@ -9,8 +9,8 @@ li x0, 4294967296 # CHECK: :[[@LINE]]:8: error: immediate must be an integer i
li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] li x0, -2147483649 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295] li t4, foo # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2147483648, 4294967295]
negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled negw x1, x2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled sext.w x3, x4 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] sll x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]
srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31] srl x2, x3, 32 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 31]

10
llvm/test/MC/RISCV/rv32i-invalid.s
View File

@ -151,8 +151,8 @@ slti a10, a2, 0x20 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction
slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction slt x32, s0, s0 # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
# RV64I mnemonics # RV64I mnemonics
addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled addiw a0, sp, 100 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled sraw t0, s2, zero # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
# Invalid operand types # Invalid operand types
xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
@ -169,9 +169,9 @@ ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
# Instruction not in the base ISA # Instruction not in the base ISA
mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'M' (Integer Multiplication and Division)
amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions)
fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point)
# Using floating point registers when integer registers are expected # Using floating point registers when integer registers are expected
addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction

10
llvm/test/MC/RISCV/rv32m-invalid.s
View File

@ -1,9 +1,9 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+m < %s 2>&1 | FileCheck %s # RUN: not llvm-mc -triple riscv32 -mattr=+m < %s 2>&1 | FileCheck %s
# RV64M instructions can't be used for RV32 # RV64M instructions can't be used for RV32
mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled mulw ra, sp, gp # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled divw tp, t0, t1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled divuw t2, s0, s2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled remw a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set
remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled remuw a3, a4, a5 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set

90
llvm/test/MC/RISCV/rv64a-valid.s
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@ -7,187 +7,185 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \ # RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s # RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# FIXME: error messages for rv32a are misleading
# CHECK-ASM-AND-OBJ: lr.d t0, (t1) # CHECK-ASM-AND-OBJ: lr.d t0, (t1)
# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10] # CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
lr.d t0, (t1) lr.d t0, (t1)
# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2) # CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14] # CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
lr.d.aq t1, (t2) lr.d.aq t1, (t2)
# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3) # CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12] # CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
lr.d.rl t2, (t3) lr.d.rl t2, (t3)
# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4) # CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16] # CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
lr.d.aqrl t3, (t4) lr.d.aqrl t3, (t4)
# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4) # CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19] # CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
sc.d t6, t5, (t4) sc.d t6, t5, (t4)
# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3) # CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d] # CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
sc.d.aq t5, t4, (t3) sc.d.aq t5, t4, (t3)
# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2) # CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b] # CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
sc.d.rl t4, t3, (t2) sc.d.rl t4, t3, (t2)
# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1) # CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e] # CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
sc.d.aqrl t3, t2, (t1) sc.d.aqrl t3, t2, (t1)
# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08] # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoswap.d a4, ra, (s0) amoswap.d a4, ra, (s0)
# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)
# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00] # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoadd.d a1, a2, (a3) amoadd.d a1, a2, (a3)
# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)
# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20] # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoxor.d a2, a3, (a4) amoxor.d a2, a3, (a4)
# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)
# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60] # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoand.d a3, a4, (a5) amoand.d a3, a4, (a5)
# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6) # CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40] # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoor.d a4, a5, (a6) amoor.d a4, a5, (a6)
# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81] # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomin.d a5, a6, (a7) amomin.d a5, a6, (a7)
# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5) # CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)
# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1] # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomax.d s7, s6, (s5) amomax.d s7, s6, (s5)
# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4) # CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)
# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1] # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amominu.d s6, s5, (s4) amominu.d s6, s5, (s4)
# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3) # CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)
# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1] # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomaxu.d s5, s4, (s3) amomaxu.d s5, s4, (s3)
# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c] # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoswap.d.aq a4, ra, (s0) amoswap.d.aq a4, ra, (s0)
# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)
# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04] # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoadd.d.aq a1, a2, (a3) amoadd.d.aq a1, a2, (a3)
# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)
# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24] # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoxor.d.aq a2, a3, (a4) amoxor.d.aq a2, a3, (a4)
# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)
# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64] # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoand.d.aq a3, a4, (a5) amoand.d.aq a3, a4, (a5)
# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6) # CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44] # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoor.d.aq a4, a5, (a6) amoor.d.aq a4, a5, (a6)
# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)
# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85] # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomin.d.aq a5, a6, (a7) amomin.d.aq a5, a6, (a7)
# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5) # CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)
# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5] # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomax.d.aq s7, s6, (s5) amomax.d.aq s7, s6, (s5)
# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4) # CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)
# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5] # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amominu.d.aq s6, s5, (s4) amominu.d.aq s6, s5, (s4)
# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3) # CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)
# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5] # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomaxu.d.aq s5, s4, (s3) amomaxu.d.aq s5, s4, (s3)
# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a] # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoswap.d.rl a4, ra, (s0) amoswap.d.rl a4, ra, (s0)
# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)
# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02] # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoadd.d.rl a1, a2, (a3) amoadd.d.rl a1, a2, (a3)
# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)
# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22] # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoxor.d.rl a2, a3, (a4) amoxor.d.rl a2, a3, (a4)
# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)
# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62] # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoand.d.rl a3, a4, (a5) amoand.d.rl a3, a4, (a5)
# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6) # CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)
# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42] # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoor.d.rl a4, a5, (a6) amoor.d.rl a4, a5, (a6)
# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)
# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83] # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomin.d.rl a5, a6, (a7) amomin.d.rl a5, a6, (a7)
# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5) # CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)
# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3] # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomax.d.rl s7, s6, (s5) amomax.d.rl s7, s6, (s5)
# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4) # CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)
# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3] # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amominu.d.rl s6, s5, (s4) amominu.d.rl s6, s5, (s4)
# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3) # CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)
# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3] # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomaxu.d.rl s5, s4, (s3) amomaxu.d.rl s5, s4, (s3)
# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0) # CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)
# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e] # CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoswap.d.aqrl a4, ra, (s0) amoswap.d.aqrl a4, ra, (s0)
# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3) # CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)
# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06] # CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoadd.d.aqrl a1, a2, (a3) amoadd.d.aqrl a1, a2, (a3)
# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4) # CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)
# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26] # CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoxor.d.aqrl a2, a3, (a4) amoxor.d.aqrl a2, a3, (a4)
# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5) # CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)
# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66] # CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoand.d.aqrl a3, a4, (a5) amoand.d.aqrl a3, a4, (a5)
# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6) # CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)
# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46] # CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amoor.d.aqrl a4, a5, (a6) amoor.d.aqrl a4, a5, (a6)
# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7) # CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)
# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87] # CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomin.d.aqrl a5, a6, (a7) amomin.d.aqrl a5, a6, (a7)
# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5) # CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)
# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7] # CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomax.d.aqrl s7, s6, (s5) amomax.d.aqrl s7, s6, (s5)
# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4) # CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)
# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7] # CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amominu.d.aqrl s6, s5, (s4) amominu.d.aqrl s6, s5, (s4)
# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3) # CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)
# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7] # CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
amomaxu.d.aqrl s5, s4, (s3) amomaxu.d.aqrl s5, s4, (s3)

28
llvm/test/MC/RISCV/rv64c-valid.s
View File

@ -10,27 +10,29 @@
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s
# RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: not llvm-mc -triple riscv32 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-RV64 %s
# FIXME: error messages for rv32c are misleading
# TODO: more exhaustive testing of immediate encoding. # TODO: more exhaustive testing of immediate encoding.
# CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp) # CHECK-ASM-AND-OBJ: c.ldsp ra, 0(sp)
# CHECK-ASM: encoding: [0x82,0x60] # CHECK-ASM: encoding: [0x82,0x60]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.ldsp ra, 0(sp) c.ldsp ra, 0(sp)
# CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp) # CHECK-ASM-AND-OBJ: c.sdsp ra, 504(sp)
# CHECK-ASM: encoding: [0x86,0xff] # CHECK-ASM: encoding: [0x86,0xff]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.sdsp ra, 504(sp) c.sdsp ra, 504(sp)
# CHECK-ASM-AND-OBJ: c.ld a4, 0(a3) # CHECK-ASM-AND-OBJ: c.ld a4, 0(a3)
# CHECK-ASM: encoding: [0x98,0x62] # CHECK-ASM: encoding: [0x98,0x62]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.ld a4, 0(a3) c.ld a4, 0(a3)
# CHECK-ASM-AND-OBJ: c.sd a5, 248(a3) # CHECK-ASM-AND-OBJ: c.sd a5, 248(a3)
# CHECK-ASM: encoding: [0xfc,0xfe] # CHECK-ASM: encoding: [0xfc,0xfe]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.sd a5, 248(a3) c.sd a5, 248(a3)
# CHECK-ASM-AND-OBJ: c.subw a3, a4 # CHECK-ASM-AND-OBJ: c.subw a3, a4
@ -38,21 +40,25 @@ c.sd a5, 248(a3)
c.subw a3, a4 c.subw a3, a4
# CHECK-ASM-AND-OBJ: c.addw a0, a2 # CHECK-ASM-AND-OBJ: c.addw a0, a2
# CHECK-ASM: encoding: [0x31,0x9d] # CHECK-ASM: encoding: [0x31,0x9d]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.addw a0, a2 c.addw a0, a2
# CHECK-ASM-AND-OBJ: c.addiw a3, -32 # CHECK-ASM-AND-OBJ: c.addiw a3, -32
# CHECK-ASM: encoding: [0x81,0x36] # CHECK-ASM: encoding: [0x81,0x36]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.addiw a3, -32 c.addiw a3, -32
# CHECK-ASM-AND-OBJ: c.addiw a3, 31 # CHECK-ASM-AND-OBJ: c.addiw a3, 31
# CHECK-ASM: encoding: [0xfd,0x26] # CHECK-ASM: encoding: [0xfd,0x26]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.addiw a3, 31 c.addiw a3, 31
# CHECK-ASM-AND-OBJ: c.slli s0, 1 # CHECK-ASM-AND-OBJ: c.slli s0, 1
# CHECK-ASM: encoding: [0x06,0x04] # CHECK-ASM: encoding: [0x06,0x04]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT: error: instruction requires the following: 'C' (Compressed Instructions)
# CHECK-NO-RV64: error: instruction requires the following: RV64I Base Instruction Set
c.slli s0, 1 c.slli s0, 1
# CHECK-ASM-AND-OBJ: c.srli a3, 63 # CHECK-ASM-AND-OBJ: c.srli a3, 63
# CHECK-ASM: encoding: [0xfd,0x92] # CHECK-ASM: encoding: [0xfd,0x92]

22
llvm/test/MC/RISCV/rv64d-valid.s
View File

@ -7,47 +7,45 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 \ # RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s # RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# FIXME: error messages for rv32d are misleading
# CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, dyn # CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, dyn
# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc2] # CHECK-ASM: encoding: [0x53,0x75,0x20,0xc2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.l.d a0, ft0, dyn fcvt.l.d a0, ft0, dyn
# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, dyn
# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc2] # CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.lu.d a1, ft1, dyn fcvt.lu.d a1, ft1, dyn
# CHECK-ASM-AND-OBJ: fmv.x.d a2, ft2 # CHECK-ASM-AND-OBJ: fmv.x.d a2, ft2
# CHECK-ASM: encoding: [0x53,0x06,0x01,0xe2] # CHECK-ASM: encoding: [0x53,0x06,0x01,0xe2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fmv.x.d a2, ft2 fmv.x.d a2, ft2
# CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, dyn # CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, dyn
# CHECK-ASM: encoding: [0xd3,0xf1,0x26,0xd2] # CHECK-ASM: encoding: [0xd3,0xf1,0x26,0xd2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.d.l ft3, a3, dyn fcvt.d.l ft3, a3, dyn
# CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, dyn # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, dyn
# CHECK-ASM: encoding: [0x53,0x72,0x37,0xd2] # CHECK-ASM: encoding: [0x53,0x72,0x37,0xd2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.d.lu ft4, a4, dyn fcvt.d.lu ft4, a4, dyn
# CHECK-ASM-AND-OBJ: fmv.d.x ft5, a5 # CHECK-ASM-AND-OBJ: fmv.d.x ft5, a5
# CHECK-ASM: encoding: [0xd3,0x82,0x07,0xf2] # CHECK-ASM: encoding: [0xd3,0x82,0x07,0xf2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fmv.d.x ft5, a5 fmv.d.x ft5, a5
# Rounding modes # Rounding modes
# CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, rne # CHECK-ASM-AND-OBJ: fcvt.d.l ft3, a3, rne
# CHECK-ASM: encoding: [0xd3,0x81,0x26,0xd2] # CHECK-ASM: encoding: [0xd3,0x81,0x26,0xd2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.d.l ft3, a3, rne fcvt.d.l ft3, a3, rne
# CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz # CHECK-ASM-AND-OBJ: fcvt.d.lu ft4, a4, rtz
# CHECK-ASM: encoding: [0x53,0x12,0x37,0xd2] # CHECK-ASM: encoding: [0x53,0x12,0x37,0xd2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.d.lu ft4, a4, rtz fcvt.d.lu ft4, a4, rtz
# CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, rdn # CHECK-ASM-AND-OBJ: fcvt.l.d a0, ft0, rdn
# CHECK-ASM: encoding: [0x53,0x25,0x20,0xc2] # CHECK-ASM: encoding: [0x53,0x25,0x20,0xc2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.l.d a0, ft0, rdn fcvt.l.d a0, ft0, rdn
# CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, rup # CHECK-ASM-AND-OBJ: fcvt.lu.d a1, ft1, rup
# CHECK-ASM: encoding: [0xd3,0xb5,0x30,0xc2] # CHECK-ASM: encoding: [0xd3,0xb5,0x30,0xc2]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.lu.d a1, ft1, rup fcvt.lu.d a1, ft1, rup

16
llvm/test/MC/RISCV/rv64dc-valid.s
View File

@ -6,24 +6,28 @@
# #
# RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: not llvm-mc -triple riscv64 -mattr=+c \
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s
# RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \
# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT %s # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s
# CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp) # CHECK-ASM-AND-OBJ: c.fldsp fs0, 504(sp)
# CHECK-ASM: encoding: [0x7e,0x34] # CHECK-ASM: encoding: [0x7e,0x34]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fldsp fs0, 504(sp) c.fldsp fs0, 504(sp)
# CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp) # CHECK-ASM-AND-OBJ: c.fsdsp fa7, 504(sp)
# CHECK-ASM: encoding: [0xc6,0xbf] # CHECK-ASM: encoding: [0xc6,0xbf]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fsdsp fa7, 504(sp) c.fsdsp fa7, 504(sp)
# CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5) # CHECK-ASM-AND-OBJ: c.fld fa3, 248(a5)
# CHECK-ASM: encoding: [0xf4,0x3f] # CHECK-ASM: encoding: [0xf4,0x3f]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fld fa3, 248(a5) c.fld fa3, 248(a5)
# CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1) # CHECK-ASM-AND-OBJ: c.fsd fa2, 248(a1)
# CHECK-ASM: encoding: [0xf0,0xbd] # CHECK-ASM: encoding: [0xf0,0xbd]
# CHECK-NO-EXT: error: instruction use requires an option to be enabled # CHECK-NO-EXT-D: error: instruction requires the following: 'D' (Double-Precision Floating-Point)
# CHECK-NO-EXT-DC: error: instruction requires the following: 'C' (Compressed Instructions), 'D' (Double-Precision Floating-Point)
c.fsd fa2, 248(a1) c.fsd fa2, 248(a1)

18
llvm/test/MC/RISCV/rv64f-valid.s
View File

@ -7,35 +7,33 @@
# RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \ # RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 \
# RUN: | FileCheck -check-prefix=CHECK-RV32 %s # RUN: | FileCheck -check-prefix=CHECK-RV32 %s
# FIXME: error messages for rv32f are misleading
# CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn # CHECK-ASM-AND-OBJ: fcvt.l.s a0, ft0, dyn
# CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0] # CHECK-ASM: encoding: [0x53,0x75,0x20,0xc0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.l.s a0, ft0, dyn fcvt.l.s a0, ft0, dyn
# CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn # CHECK-ASM-AND-OBJ: fcvt.lu.s a1, ft1, dyn
# CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0] # CHECK-ASM: encoding: [0xd3,0xf5,0x30,0xc0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.lu.s a1, ft1, dyn fcvt.lu.s a1, ft1, dyn
# CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn # CHECK-ASM-AND-OBJ: fcvt.s.l ft2, a2, dyn
# CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0] # CHECK-ASM: encoding: [0x53,0x71,0x26,0xd0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.s.l ft2, a2, dyn fcvt.s.l ft2, a2, dyn
# CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn # CHECK-ASM-AND-OBJ: fcvt.s.lu ft3, a3, dyn
# CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0] # CHECK-ASM: encoding: [0xd3,0xf1,0x36,0xd0]
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.s.lu ft3, a3, dyn fcvt.s.lu ft3, a3, dyn
# Rounding modes # Rounding modes
# CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne # CHECK-ASM-AND-OBJ: fcvt.l.s a4, ft4, rne
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.l.s a4, ft4, rne fcvt.l.s a4, ft4, rne
# CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz # CHECK-ASM-AND-OBJ: fcvt.lu.s a5, ft5, rtz
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.lu.s a5, ft5, rtz fcvt.lu.s a5, ft5, rtz
# CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn # CHECK-ASM-AND-OBJ: fcvt.s.l ft6, a6, rdn
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.s.l ft6, a6, rdn fcvt.s.l ft6, a6, rdn
# CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup # CHECK-ASM-AND-OBJ: fcvt.s.lu ft7, a7, rup
# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled # CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set
fcvt.s.lu ft7, a7, rup fcvt.s.lu ft7, a7, rup

6
llvm/test/MC/RISCV/rv64i-aliases-invalid.s
View File

@ -5,9 +5,9 @@
li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand li t5, 0x10000000000000000 # CHECK: :[[@LINE]]:8: error: unknown operand
li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer li t4, foo # CHECK: :[[@LINE]]:8: error: operand must be a constant 64-bit integer
rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled rdinstreth x29 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled rdcycleh x27 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled rdtimeh x28 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set
sll x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] sll x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]
srl x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63] srl x2, x3, 64 # CHECK: :[[@LINE]]:13: error: immediate must be an integer in the range [0, 63]