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[AMDGPU] gfx1010 v_interp_* instructions 

Differential Revision: https://reviews.llvm.org/D61703

llvm-svn: 360364
This commit is contained in:
Stanislav Mekhanoshin 2019-05-09 18:38:55 +00:00
parent b1271cceca
commit a76da34b1d
1 changed files with 11 additions and 6 deletions
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17
llvm/lib/Target/AMDGPU/SIInstrInfo.td
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@ -2008,13 +2008,12 @@ class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
let isCodeGenOnly = 1;
}
// FIXME-GFX10: WIP.
class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
string asm> :
string asm, int encodingFamily> :
VINTRPCommon <outs, ins, asm, []>,
VINTRPe <op>,
SIMCInstr<opName, SIEncodingFamily.SI> {
let AssemblerPredicate = SIAssemblerPredicate;
let DecoderNamespace = "GFX6GFX7";
SIMCInstr<opName, encodingFamily> {
let DisableDecoder = DisableSIDecoder;
}
@ -2028,15 +2027,21 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
let DisableDecoder = DisableVIDecoder;
}
// FIXME-GFX10: WIP.
multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
list<dag> pattern = []> {
def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
def _si : VINTRP_Real_si <op, NAME, outs, ins, asm, SIEncodingFamily.SI>;
} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
}
let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
def _gfx10 : VINTRP_Real_si<op, NAME, outs, ins, asm, SIEncodingFamily.GFX10>;
} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
}
//===----------------------------------------------------------------------===//
// Vector instruction mappings
//===----------------------------------------------------------------------===//