[RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
The DAGCombiner changes led to a different schedule. llvm-svn: 346496
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@ -997,14 +997,14 @@ define void @caller_large_scalar_ret() nounwind {
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define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
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; RV32I-FPELIM-LABEL: callee_large_struct_ret:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi a1, zero, 4
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; RV32I-FPELIM-NEXT: sw a1, 12(a0)
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; RV32I-FPELIM-NEXT: addi a1, zero, 3
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; RV32I-FPELIM-NEXT: sw a1, 8(a0)
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; RV32I-FPELIM-NEXT: addi a1, zero, 2
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; RV32I-FPELIM-NEXT: sw a1, 4(a0)
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; RV32I-FPELIM-NEXT: addi a1, zero, 1
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; RV32I-FPELIM-NEXT: sw a1, 0(a0)
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; RV32I-FPELIM-NEXT: addi a1, zero, 3
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; RV32I-FPELIM-NEXT: sw a1, 8(a0)
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; RV32I-FPELIM-NEXT: addi a1, zero, 4
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; RV32I-FPELIM-NEXT: sw a1, 12(a0)
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: callee_large_struct_ret:
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@ -1013,14 +1013,14 @@ define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) no
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; RV32I-WITHFP-NEXT: sw ra, 12(sp)
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; RV32I-WITHFP-NEXT: sw s0, 8(sp)
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; RV32I-WITHFP-NEXT: addi s0, sp, 16
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; RV32I-WITHFP-NEXT: addi a1, zero, 4
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; RV32I-WITHFP-NEXT: sw a1, 12(a0)
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; RV32I-WITHFP-NEXT: addi a1, zero, 3
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; RV32I-WITHFP-NEXT: sw a1, 8(a0)
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; RV32I-WITHFP-NEXT: addi a1, zero, 2
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; RV32I-WITHFP-NEXT: sw a1, 4(a0)
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; RV32I-WITHFP-NEXT: addi a1, zero, 1
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; RV32I-WITHFP-NEXT: sw a1, 0(a0)
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; RV32I-WITHFP-NEXT: addi a1, zero, 3
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; RV32I-WITHFP-NEXT: sw a1, 8(a0)
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; RV32I-WITHFP-NEXT: addi a1, zero, 4
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; RV32I-WITHFP-NEXT: sw a1, 12(a0)
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; RV32I-WITHFP-NEXT: lw s0, 8(sp)
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; RV32I-WITHFP-NEXT: lw ra, 12(sp)
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; RV32I-WITHFP-NEXT: addi sp, sp, 16
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