From aa1b22db0f51bc053ff16874ba1be3bacec53cf8 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad@amd.com>
Date: Wed, 6 Apr 2022 10:49:43 +0100
Subject: [PATCH] [AMDGPU] Add a test for setting EXTRA_LDS_SIZE in pixel
 shaders

---
 llvm/test/CodeGen/AMDGPU/extra-lds-size.ll | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/extra-lds-size.ll

diff --git a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
new file mode 100644
index 000000000000..0df9d3e41d0e
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-PAL %s
+; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10-MESA %s
+
+; Check EXTRA_LDS_SIZE in SPI_SHADER_PGM_RSRC2_PS.
+
+; GFX10-PAL: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x800
+
+; GFX10-MESA: .long 45100
+; GFX10-MESA-NEXT: .long 2048
+
+@lds = internal addrspace(3) global [4096 x i8] undef
+
+define amdgpu_ps void @global_store_saddr_uniform_ptr_in_vgprs(i32 %voffset) {
+  %ptr = getelementptr [4096 x i8], [4096 x i8] addrspace(3)* @lds, i32 0, i32 %voffset
+  store i8 0, i8 addrspace(3)* %ptr
+  ret void
+}