OSchip
/
llvm-project
mirror of https://github.com/THU-DSP-LAB/llvm-project.git
13
0
Fork 6
Code Issues Packages Projects Releases Wiki Activity

[AVX512] Simplify the instruction defintion for VEXTRACT. NFCI 

The comment about why we couldn't use avx512_maskable appears to have been incorrect.

llvm-svn: 310808
This commit is contained in:
Craig Topper 2017-08-14 01:53:10 +00:00
parent 37b2286564
commit aadec7078e
1 changed files with 16 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
llvm/lib/Target/X86/X86InstrAVX512.td
View File

@ -656,12 +656,11 @@ multiclass vextract_for_size<int Opcode,
// use AVX512_maskable_in_asm (AVX512_maskable can't be used due to // use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
// vextract_extract), we interesting only in patterns without mask, // vextract_extract), we interesting only in patterns without mask,
// intrinsics pattern match generated bellow. // intrinsics pattern match generated bellow.
defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst), defm rr : AVX512_maskable<Opcode, MRMDestReg, To, (outs To.RC:$dst),
(ins From.RC:$src1, u8imm:$idx), (ins From.RC:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts, "vextract" # To.EltTypeName # "x" # To.NumElts,
"$idx, $src1", "$src1, $idx", "$idx, $src1", "$src1, $idx",
[(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1), (vextract_extract:$idx (From.VT From.RC:$src1), (iPTR imm))>,
(iPTR imm)))]>,
AVX512AIi8Base, EVEX; AVX512AIi8Base, EVEX;
def mr : AVX512AIi8<Opcode, MRMDestMem, (outs), def mr : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx), (ins To.MemOp:$dst, From.RC:$src1, u8imm:$idx),
@ -680,24 +679,6 @@ multiclass vextract_for_size<int Opcode,
"$dst {${mask}}, $src1, $idx}", "$dst {${mask}}, $src1, $idx}",
[]>, EVEX_K, EVEX; []>, EVEX_K, EVEX;
} }
def : Pat<(To.VT (vselect To.KRCWM:$mask,
(vextract_extract:$ext (From.VT From.RC:$src1),
(iPTR imm)),
To.RC:$src0)),
(!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
From.ZSuffix # "rrk")
To.RC:$src0, To.KRCWM:$mask, From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext))>;
def : Pat<(To.VT (vselect To.KRCWM:$mask,
(vextract_extract:$ext (From.VT From.RC:$src1),
(iPTR imm)),
To.ImmAllZerosV)),
(!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
From.ZSuffix # "rrkz")
To.KRCWM:$mask, From.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext))>;
} }
// Codegen pattern for the alternative types // Codegen pattern for the alternative types
@ -718,18 +699,20 @@ multiclass vextract_for_size_lowering<string InstrStr, X86VectorVTInfo From,
multiclass vextract_for_type<ValueType EltVT32, int Opcode128, multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
ValueType EltVT64, int Opcode256> { ValueType EltVT64, int Opcode256> {
defm NAME # "32x4Z" : vextract_for_size<Opcode128, let Predicates = [HasAVX512] in {
X86VectorVTInfo<16, EltVT32, VR512>, defm NAME # "32x4Z" : vextract_for_size<Opcode128,
X86VectorVTInfo< 4, EltVT32, VR128X>, X86VectorVTInfo<16, EltVT32, VR512>,
vextract128_extract, X86VectorVTInfo< 4, EltVT32, VR128X>,
EXTRACT_get_vextract128_imm>, vextract128_extract,
EVEX_V512, EVEX_CD8<32, CD8VT4>; EXTRACT_get_vextract128_imm>,
defm NAME # "64x4Z" : vextract_for_size<Opcode256, EVEX_V512, EVEX_CD8<32, CD8VT4>;
X86VectorVTInfo< 8, EltVT64, VR512>, defm NAME # "64x4Z" : vextract_for_size<Opcode256,
X86VectorVTInfo< 4, EltVT64, VR256X>, X86VectorVTInfo< 8, EltVT64, VR512>,
vextract256_extract, X86VectorVTInfo< 4, EltVT64, VR256X>,
EXTRACT_get_vextract256_imm>, vextract256_extract,
VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>; EXTRACT_get_vextract256_imm>,
VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
}
let Predicates = [HasVLX] in let Predicates = [HasVLX] in
defm NAME # "32x4Z256" : vextract_for_size<Opcode128, defm NAME # "32x4Z256" : vextract_for_size<Opcode128,
X86VectorVTInfo< 8, EltVT32, VR256X>, X86VectorVTInfo< 8, EltVT32, VR256X>,