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Split the file MipsAsmBackend.cpp in Split the file MipsAsmBackend.cpp and Split the file MipsAsmBackend.h. 

Differential Revision: http://llvm-reviews.chandlerc.com/D3134

llvm-svn: 204921
This commit is contained in:
Zoran Jovanovic 2014-03-27 12:38:40 +00:00
parent 82540e9ef8
commit ada38ef61b
2 changed files with 237 additions and 191 deletions
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336
llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
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@ -1,4 +1,4 @@
//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
@ -7,12 +7,13 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file implements the MipsAsmBackend and MipsELFObjectWriter classes. // This file implements the MipsAsmBackend class.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
#include "MipsFixupKinds.h" #include "MCTargetDesc/MipsFixupKinds.h"
#include "MCTargetDesc/MipsAsmBackend.h"
#include "MCTargetDesc/MipsMCTargetDesc.h" #include "MCTargetDesc/MipsMCTargetDesc.h"
#include "llvm/MC/MCAsmBackend.h" #include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCAssembler.h" #include "llvm/MC/MCAssembler.h"
@ -106,208 +107,162 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
return Value; return Value;
} }
namespace { MCObjectWriter *MipsAsmBackend::createObjectWriter(raw_ostream &OS) const {
class MipsAsmBackend : public MCAsmBackend { return createMipsELFObjectWriter(OS,
Triple::OSType OSType; MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
bool IsLittle; // Big or little endian }
bool Is64Bit; // 32 or 64 bit words
public: /// ApplyFixup - Apply the \p Value for given \p Fixup into the provided
MipsAsmBackend(const Target &T, Triple::OSType _OSType, /// data fragment, at the offset specified by the fixup and following the
bool _isLittle, bool _is64Bit) /// fixup kind as appropriate.
:MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {} void MipsAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
unsigned DataSize, uint64_t Value) const {
MCFixupKind Kind = Fixup.getKind();
Value = adjustFixupValue(Fixup, Value);
MCObjectWriter *createObjectWriter(raw_ostream &OS) const { if (!Value)
return createMipsELFObjectWriter(OS, return; // Doesn't change encoding.
MCELFObjectTargetWriter::getOSABI(OSType), IsLittle, Is64Bit);
// Where do we start in the object
unsigned Offset = Fixup.getOffset();
// Number of bytes we need to fixup
unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
// Used to point to big endian bytes
unsigned FullSize;
switch ((unsigned)Kind) {
case FK_Data_2:
case Mips::fixup_Mips_16:
FullSize = 2;
break;
case FK_Data_8:
case Mips::fixup_Mips_64:
FullSize = 8;
break;
case FK_Data_4:
default:
FullSize = 4;
break;
} }
/// ApplyFixup - Apply the \p Value for given \p Fixup into the provided // Grab current value, if any, from bits.
/// data fragment, at the offset specified by the fixup and following the uint64_t CurVal = 0;
/// fixup kind as appropriate.
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value) const {
MCFixupKind Kind = Fixup.getKind();
Value = adjustFixupValue(Fixup, Value);
if (!Value) for (unsigned i = 0; i != NumBytes; ++i) {
return; // Doesn't change encoding. unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
// Where do we start in the object
unsigned Offset = Fixup.getOffset();
// Number of bytes we need to fixup
unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
// Used to point to big endian bytes
unsigned FullSize;
switch ((unsigned)Kind) {
case FK_Data_2:
case Mips::fixup_Mips_16:
FullSize = 2;
break;
case FK_Data_8:
case Mips::fixup_Mips_64:
FullSize = 8;
break;
case FK_Data_4:
default:
FullSize = 4;
break;
}
// Grab current value, if any, from bits.
uint64_t CurVal = 0;
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
}
uint64_t Mask = ((uint64_t)(-1) >>
(64 - getFixupKindInfo(Kind).TargetSize));
CurVal |= Value & Mask;
// Write out the fixed up bytes back to the code/data bits.
for (unsigned i = 0; i != NumBytes; ++i) {
unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
}
} }
unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; } uint64_t Mask = ((uint64_t)(-1) >>
(64 - getFixupKindInfo(Kind).TargetSize));
CurVal |= Value & Mask;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { // Write out the fixed up bytes back to the code/data bits.
const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = { for (unsigned i = 0; i != NumBytes; ++i) {
// This table *must* be in same the order of fixup_* kinds in unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
// MipsFixupKinds.h. Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
//
// name offset bits flags
{ "fixup_Mips_16", 0, 16, 0 },
{ "fixup_Mips_32", 0, 32, 0 },
{ "fixup_Mips_REL32", 0, 32, 0 },
{ "fixup_Mips_26", 0, 26, 0 },
{ "fixup_Mips_HI16", 0, 16, 0 },
{ "fixup_Mips_LO16", 0, 16, 0 },
{ "fixup_Mips_GPREL16", 0, 16, 0 },
{ "fixup_Mips_LITERAL", 0, 16, 0 },
{ "fixup_Mips_GOT_Global", 0, 16, 0 },
{ "fixup_Mips_GOT_Local", 0, 16, 0 },
{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_CALL16", 0, 16, 0 },
{ "fixup_Mips_GPREL32", 0, 32, 0 },
{ "fixup_Mips_SHIFT5", 6, 5, 0 },
{ "fixup_Mips_SHIFT6", 6, 5, 0 },
{ "fixup_Mips_64", 0, 64, 0 },
{ "fixup_Mips_TLSGD", 0, 16, 0 },
{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
{ "fixup_Mips_TLSLDM", 0, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
{ "fixup_Mips_HIGHER", 0, 16, 0 },
{ "fixup_Mips_HIGHEST", 0, 16, 0 },
{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
};
if (Kind < FirstTargetFixupKind)
return MCAsmBackend::getFixupKindInfo(Kind);
assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
"Invalid kind!");
return Infos[Kind - FirstTargetFixupKind];
} }
}
/// @name Target Relaxation Interfaces const MCFixupKindInfo &MipsAsmBackend::
/// @{ getFixupKindInfo(MCFixupKind Kind) const {
const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
// This table *must* be in same the order of fixup_* kinds in
// MipsFixupKinds.h.
//
// name offset bits flags
{ "fixup_Mips_16", 0, 16, 0 },
{ "fixup_Mips_32", 0, 32, 0 },
{ "fixup_Mips_REL32", 0, 32, 0 },
{ "fixup_Mips_26", 0, 26, 0 },
{ "fixup_Mips_HI16", 0, 16, 0 },
{ "fixup_Mips_LO16", 0, 16, 0 },
{ "fixup_Mips_GPREL16", 0, 16, 0 },
{ "fixup_Mips_LITERAL", 0, 16, 0 },
{ "fixup_Mips_GOT_Global", 0, 16, 0 },
{ "fixup_Mips_GOT_Local", 0, 16, 0 },
{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_CALL16", 0, 16, 0 },
{ "fixup_Mips_GPREL32", 0, 32, 0 },
{ "fixup_Mips_SHIFT5", 6, 5, 0 },
{ "fixup_Mips_SHIFT6", 6, 5, 0 },
{ "fixup_Mips_64", 0, 64, 0 },
{ "fixup_Mips_TLSGD", 0, 16, 0 },
{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
{ "fixup_Mips_TLSLDM", 0, 16, 0 },
{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_Mips_GPOFF_HI", 0, 16, 0 },
{ "fixup_Mips_GPOFF_LO", 0, 16, 0 },
{ "fixup_Mips_GOT_PAGE", 0, 16, 0 },
{ "fixup_Mips_GOT_OFST", 0, 16, 0 },
{ "fixup_Mips_GOT_DISP", 0, 16, 0 },
{ "fixup_Mips_HIGHER", 0, 16, 0 },
{ "fixup_Mips_HIGHEST", 0, 16, 0 },
{ "fixup_Mips_GOT_HI16", 0, 16, 0 },
{ "fixup_Mips_GOT_LO16", 0, 16, 0 },
{ "fixup_Mips_CALL_HI16", 0, 16, 0 },
{ "fixup_Mips_CALL_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_26_S1", 0, 26, 0 },
{ "fixup_MICROMIPS_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT16", 0, 16, 0 },
{ "fixup_MICROMIPS_PC16_S1", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_MICROMIPS_CALL16", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_DISP", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_PAGE", 0, 16, 0 },
{ "fixup_MICROMIPS_GOT_OFST", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_GD", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_LDM", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 },
{ "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }
};
/// MayNeedRelaxation - Check whether the given instruction may need if (Kind < FirstTargetFixupKind)
/// relaxation. return MCAsmBackend::getFixupKindInfo(Kind);
///
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const {
return false;
}
/// fixupNeedsRelaxation - Target specific predicate for whether a given assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
/// fixup requires the associated instruction to be relaxed. "Invalid kind!");
bool fixupNeedsRelaxation(const MCFixup &Fixup, return Infos[Kind - FirstTargetFixupKind];
uint64_t Value, }
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const {
// FIXME.
assert(0 && "RelaxInstruction() unimplemented");
return false;
}
/// RelaxInstruction - Relax the instruction in the given fragment /// WriteNopData - Write an (optimal) nop sequence of Count bytes
/// to the next wider instruction. /// to the given output. If the target cannot generate such a sequence,
/// /// it should return an error.
/// \param Inst - The instruction to relax, which may be the same ///
/// as the output. /// \return - True on success.
/// \param [out] Res On return, the relaxed instruction. bool MipsAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
void relaxInstruction(const MCInst &Inst, MCInst &Res) const { // Check for a less than instruction size number of bytes
} // FIXME: 16 bit instructions are not handled yet here.
// We shouldn't be using a hard coded number for instruction size.
if (Count % 4) return false;
/// @} uint64_t NumNops = Count / 4;
for (uint64_t i = 0; i != NumNops; ++i)
OW->Write32(0);
return true;
}
/// WriteNopData - Write an (optimal) nop sequence of Count bytes /// processFixupValue - Target hook to process the literal value of a fixup
/// to the given output. If the target cannot generate such a sequence, /// if necessary.
/// it should return an error. void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
/// const MCAsmLayout &Layout,
/// \return - True on success. const MCFixup &Fixup,
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { const MCFragment *DF,
// Check for a less than instruction size number of bytes MCValue &Target,
// FIXME: 16 bit instructions are not handled yet here. uint64_t &Value,
// We shouldn't be using a hard coded number for instruction size. bool &IsResolved) {
if (Count % 4) return false; // At this point we'll ignore the value returned by adjustFixupValue as
// we are only checking if the fixup can be applied correctly. We have
uint64_t NumNops = Count / 4; // access to MCContext from here which allows us to report a fatal error
for (uint64_t i = 0; i != NumNops; ++i) // with *possibly* a source code location.
OW->Write32(0); (void)adjustFixupValue(Fixup, Value, &Asm.getContext());
return true; }
}
/// processFixupValue - Target hook to process the literal value of a fixup
/// if necessary.
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
MCValue &Target, uint64_t &Value,
bool &IsResolved) {
// At this point we'll ignore the value returned by adjustFixupValue as
// we are only checking if the fixup can be applied correctly. We have
// access to MCContext from here which allows us to report a fatal error
// with *possibly* a source code location.
(void)adjustFixupValue(Fixup, Value, &Asm.getContext());
}
}; // class MipsAsmBackend
} // namespace
// MCAsmBackend // MCAsmBackend
MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
@ -341,4 +296,3 @@ MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
return new MipsAsmBackend(T, Triple(TT).getOS(), return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/false, /*Is64Bit*/true); /*IsLittle*/false, /*Is64Bit*/true);
} }

92
llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.h Normal file
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@ -0,0 +1,92 @@
//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines the MipsAsmBackend class.
//
//===----------------------------------------------------------------------===//
//
#ifndef MIPSASMBACKEND_H
#define MIPSASMBACKEND_H
#include "MCTargetDesc/MipsFixupKinds.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/ADT/Triple.h"
namespace llvm {
class MCAssembler;
class MCFixupKindInfo;
class Target;
class MCObjectWriter;
class MipsAsmBackend : public MCAsmBackend {
Triple::OSType OSType;
bool IsLittle; // Big or little endian
bool Is64Bit; // 32 or 64 bit words
public:
MipsAsmBackend(const Target &T, Triple::OSType _OSType, bool _isLittle,
bool _is64Bit)
: MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle),
Is64Bit(_is64Bit) {}
MCObjectWriter *createObjectWriter(raw_ostream &OS) const;
void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
uint64_t Value) const;
const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
unsigned getNumFixupKinds() const {
return Mips::NumTargetFixupKinds;
}
/// @name Target Relaxation Interfaces
/// @{
/// MayNeedRelaxation - Check whether the given instruction may need
/// relaxation.
///
/// \param Inst - The instruction to test.
bool mayNeedRelaxation(const MCInst &Inst) const {
return false;
}
/// fixupNeedsRelaxation - Target specific predicate for whether a given
/// fixup requires the associated instruction to be relaxed.
bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
const MCRelaxableFragment *DF,
const MCAsmLayout &Layout) const {
// FIXME.
assert(0 && "RelaxInstruction() unimplemented");
return false;
}
/// RelaxInstruction - Relax the instruction in the given fragment
/// to the next wider instruction.
///
/// \param Inst - The instruction to relax, which may be the same
/// as the output.
/// \param [out] Res On return, the relaxed instruction.
void relaxInstruction(const MCInst &Inst, MCInst &Res) const {}
/// @}
bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
const MCFixup &Fixup, const MCFragment *DF,
MCValue &Target, uint64_t &Value, bool &IsResolved);
}; // class MipsAsmBackend
} // namespace
#endif